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| july 2007 rev 3 1/81 1 str750fxx str751fxx str752fxx str755fxx arm7tdmi-s? 32-bit mcu with flas h, smi, 3 std 16-bit timers, pwm timer, fast 10-bit adc, i2c, uart, ssp, usb and can features core ? arm7tdmi-s 32-bit risc cpu ? 54 dmips @ 60 mhz memories ? up to 256 kb flash program memory (10k w/e cycles, retention 20 yrs @ 85c) ? 16 kb read-while-write flash for data (100k w/e cycles, retention 20 yrs@ 85c) ? flash data readout and write protection ? 16kbytes embedded high speed sram ? memory mapped interface (smi) to ext. serial flash (64 mb) w. boot capability clock, reset and supply management ? single supply 3.3v 10% or 5v 10% ? embedded 1.8v voltage regulators ? int. rc for fast start-up and backup clock ? up to 60 mhz operation using internal pll with 4 or 8 mhz crystal/ceramic osc. ? smart low power modes: slow, wfi, stop and standby with backup registers ? real time clock, driven by low power internal rc or 32.768 khz dedicated osc, for clock-calendar and auto wake-up nested interr upt controller ? fast interrupt handling with 32 vectors ? 16 irq priorities, 2 maskable fiq sources ? 16 external interrupt / wake-up lines dma ? 4-channel dma controller ? circular buffer management ? support for uart, ssp, timers, adc 6 timers ? 16-bit watchdog timer (wdg) ? 16-bit timer for system timebase functions ? 3 synchronizable timers each with up to 2 input captures and 2 output compare/pwms. ? 16-bit 6-ch. synchronizable pwm timer ? dead time generation, edge/center-aligned waveforms and emergency stop ? ideal for induction/brushless dc motors 8 communications interfaces ?1 i 2 c interface ? 3 hispeed uarts w. modem/lin capability ? 2 ssp interfaces (spi or ssi) up to 16 mb/s ? 1 can interface (2.0b active) ? 1 usb full-speed 12 mb/s interface with 8 configurable endpoint sizes 10-bit a/d converter ? 16/11 chan. with prog. scan mode & fifo ? programmable analog watchdog feature ? conversion time: min. 3.75 s ? start conversion can be triggered by timers up to 72/38 i/o ports ? 72/38 gpios with high sink capabilities ? atomic bit set and res operations table 1. device summary reference root part number str750fxx str750fv0, str750fv1, str750fv2 str751fxx str751fr0, str751fr1, str751fr2 str752fxx str752fr0, str752fr1, str752fr2 str755fxx str755fr0, str755fr1, str755fr2 str755fv0, str755fv1, str755fv2 lqfp64 10x10 mm lqfp100 14 x 14 mm lfbga64 8 x 8 x 1.7 mm lfbga100 10 x 10 x 1.7 mm www.st.com
contents str750fxx str751fxx str752fxx str755fxx 2/81 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.0.1 pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.6 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.7 i/o characteristics versus the various power schemes (3.3v or 5.0v) . 29 5.1.8 current consumption measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 34 5.3.3 embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 str750fxx str751fxx str752fxx str755fxx contents 3/81 5.3.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.9 tb and tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.11 usb characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 description str750fxx str751fxx str752fxx str755fxx 4/81 1 description the str750 family of 32-bit microcontrollers combines the industry-standard arm7tdmi? 32-bit risc core, featuring high performance, very low power, and very dense code, with a comprehensive set of peripherals and st's latest 0.18 embedded flash technology. the str750 family comprises a range of devices integrating a common set of peripherals as well as usb, can and some key innovations like clock failure detection and an advanced motor control timer. it supports both 3.3v and 5v, and it is also available in an extended temperature range (-40 to +105c). this makes it a genuine general purpose microcontroller family, suitable for a wide range of applications: appliances, brushless motor drives usb peripherals, ups, alarm systems programmable logic controllers, circuit breakers, inverters medical and portable equipment 2 device overview table 2. device overview features str755fr0 str755fr1 str755fr2 str751fr0/ str751fr1/ str751fr2 str752fr0/ str752fr1/ str752fr2 str755fv0 str755fv1/ str755fv2 str750fv0/ str750fv1/ str750fv2 flash - bank 0 (bytes) 64k/128k/256k flash - bank 1 (bytes) 16k rww ram (bytes) 16k operating temp. -40 to +85c / -40 to +105c (see ta bl e 4 9 ) common peripherals 3 uarts, 2 ssps, 1 i2c, 3 timers 1 pwm timer, 38 i/os 13 wake-up lines, 11 a/d channels 3 uarts, 2 ssps, 1 i 2 c, 3 timers 1 pwm timer, 72 i/os 15 wake-up lines, 16 a/d channels usb/can peripherals none usb can none usb+can operating voltage 3.3v or 5v 3.3v 3.3v or 5v packages ( x ) t =lqfp64 10x10, h =lfbga64 t =lqfp100 14x14, h =lfbga100 str750fxx str751fxx str752fxx str755fxx introduction 5/81 3 introduction this datasheet contains the description of th e str750f family features, pinout, electrical characteristics, mechanical data and ordering information. for complete information on the microcontroller memory, registers and peripherals. please refer to the str750f reference manual. for information on the arm7tdmi-s core please refer to the arm7tdmi-s technical reference manual available from arm ltd. for information on programming, erasing and protection of the internal flash memory please refer to the str7 flash programming reference manual for information on third-party development tools, please refer to the http://www.st.com/mcu website. 3.1 functional description the str750f family includes devices in 2 package sizes: 64-pin and 100-pin. both types have the following common features: arm7tdmi-s tm core with embedded flash & ram str750f family has an embedded arm core and is therefore compatible with all arm tools and software. it combines the high performance arm7tdmi-s tm cpu with an extensive range of peripheral fu nctions and enhanced i/ o capabilities. all devices have on-chip high- speed single voltage flash memory and high-speed ram. figure 1 shows the general block diagram of the device family. embedded flash memory up to 256 kbytes of embedded flash is available in bank 0 for storing programs and data. an additional bank 1 provides 16 kbytes of rww (read while write) memory allowing it to be erased/programmed on-the-fly. this partitioning feature is ideal for storing application parameters. when configured in burst mode, access to flash memory is performed at cpu clock speed with 0 wait states for sequential accesses and 1 wait state for random access (maximum 60 mhz). when not configured in burst mode, acce ss to flash memory is performed at cpu clock speed with 0 wait states (maximum 32 mhz) embedded sram 16 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. enhanced interrupt controller (eic) in addition to the standard arm interrupt controller, the str750f embeds a nested interrupt controller able to handle up to 32 vectors and 16 priority levels. this additional hardware block provides flexible interrupt management features with minimal interrupt latency. introduction str750fxx str751fxx str752fxx str755fxx 6/81 serial memory interface (smi) the serial memory interface is directly able to access up to 4 serial flash devices. it can be used to access data, execute code directly or boot the application from external memory. the memory is addressed as 4 banks of up to 16 mbytes each. clocks and start-up after reset or when exiting from low power m ode, the cpu is clocked immediately by an internal rc oscillator (freeosc) at a frequency centered ar ound 5 mhz, so the application code can start executing without delay. in para llel, the 4/8 mhz oscillator is enabled and its stabilization time is monitore d using a dedicated counter. an oscillator failure de tection is implemented: when the clock disappears on the xt1 pin, the circuit automatically switches to the freeosc oscillator and an interrupt is generated. in run mode, the ahb and apb clock speeds can be set at a large number of different frequencies thanks to the pll and various prescalers: up to 60 mhz for ahb and up to 32 mhz for apb when fetching from flash (64 mh z and 32 mhz when fe tching from sram). in slow mode, the ahb clock can be significantly decreased to reduce power consumption. the built-in clock controller also provides the 48 mhz usb clock directly without any extra oscillators or pll. for instance, starting from the 4 mhz crystal source, it is possible to obtain in parallel 60 mhz for the ahb clock, 48 mhz for the usb clock and 30 mhz for the apb peripherals. boot modes at start-up, boot pins are used to select one of five boot options: boot from internal flash boot from external serial flash memory boot from internal boot loader boot from internal sram booting from smi memory allows booting from a serial flash. this way, a specific boot monitor can be implemented. alternatively, the str750f can boot from the internal boot loader that implements a boot from uart. power supply schemes you can connect the device in any of the following ways depending on your application. power scheme 1: single external 3.3v power source . in this configuration the v core supply required for the internal logic is generated internally by the main voltage regulator and the v backup supply is generated internally by the low power voltage regulator. this scheme has the advantage of requiring only one 3.3v power source. power scheme 2: dual external 3.3v and 1.8v power sources. in this configuration, the internal voltage regulators are switched off by forcing the vreg_dis pin to high level. v core is provided externally through the v 18 and v 18reg power pins and v backup through the v 18_bkp pin. this scheme is intended to save power consumption for applications which already provide an 1.8v power supply. power scheme 3: single external 5.0v power source. in this configuration the v core supply required for the internal logic is generated internally by the main voltage str750fxx str751fxx str752fxx str755fxx introduction 7/81 regulator and the v backup supply is generated internally by the low power voltage regulator. this scheme has the advantage of requiring only one 5.0v power source. power scheme 4: dual external 5.0v and 1.8v power sources. in this configuration, the internal voltage regulators are switched off, by forcing the vreg_dis pin to high level. v core is provided externally through the v 18 and v 18reg power pins and v backup through the v 18_bkp pin. this scheme is intended to provide 5v i/o capability. caution: when powered by 5.0v, the usb peripheral cannot operate. low power modes the str750f supports 5 low power modes, slow, pcg, wfi, stop and standby. slow mode: the system clock speed is reduced. alternatively, the pll and the main oscillator can be stopped and the device is driven by a low power clock (f rtc ). the clock is either an external 32.768 khz osc illator or the internal low power rc oscillator. pcg mode (peripheral clock gating mode): when the peripherals are not used, their apb clocks are gated to optimi ze the power consumption. wfi mode (wait for interrupts): only th e cpu clock is stopped, all peripherals continue to work and can wake-up the cpu when irqs occur. stop mode: all clocks/peripherals are disabled. it is also possible to disable the oscillators and the main voltage regulator (in this case the v core is entirely powered by v 18_bkp ). this mode is intended to achieve the lowest power consumption with sram and registers contents retained. th e system can be woken up by any of the external interrupts / wake-up lines or by the rtc timer which can optionally be kept running. the rtc can be clocked either by the 32.768 khz crystal or the low power rc oscillator. alternatively, stop mode gives flexibility to k eep the either main o scillator, or the flash or the main voltage regulator enabled when a fast start after wake-up is preferred (at the cost of some extra power consumption). standby mode: this mode (only available in single supply power schemes) is intended to achieve the lowest power consumption even when the temperature is increasing. the digital power supply (v core ) is completely remo ved (no leakage even at high ambient temperature). sram and all register contents are lost. only the rtc remains powered by v 18_bkp . the str750f can be switched back from standby to run mode by a trigger event on the wkp_stdby pin or an alarm timeout on the rtc counter. caution: it is important to bear in mind that it is forbidden to remove power from the v dd_io power supply in any of the low power modes (even in standby mode). dma the flexible 4-channel general-purpose dma is able to manage memory to memory, peripheral to memory and memory to peripheral transfers. the dma controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. the dma can be used with the main peripherals: uart0, ssp0, motor control pwm timer (pwm), standard timer tim0 and adc. rtc (real time clock) the real time clock provides a set of contin uously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a introduction str750fxx str751fxx str752fxx str755fxx 8/81 periodic interrupt. it is clocked by an external 32.768 khz oscillator or the internal low power rc oscillator. the rc has a typical freq uency of 300 khz and can be calibrated. wdg (watchdog timer) the watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. it can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management. timebase timer (tb) the timebase timer is based on a 16-bit auto-reload counter and not connected to the i/o pins. it can be used for software triggering, or to implement the scheduler of a real time operating system. synchronizable standard timers (tim2:0) the three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). they can work together with the pwm timer via the timer link feature for synchronization or event chaining. in reset state, timer alternate function i/os are connected to the same i/o ports in both 64-pin and 100-pin devices. to optimize timer functions in 64-pin devices, timer alternate function i/os can be connected, or ?remapped?, to other i/o ports as summarized in ta b l e 3 and detailed in ta b l e 6 . this remapping is done by the application via a control register. any of the standard timers can be used to generate pwm outputs. one timer (tim0) is mapped to a dma channel. motor control pwm timer (pwm) the motor control pwm timer (pwm) can be seen as a three-phase pwm multiplexed on 6 channels. the 16-bit pwm generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. it has many features in common with the standard tim timers which has the same architecture and it can work together with the tim timers via the timer link feature for synchronization or event chaining.the pwm timer is mapped to a dma channel. table 3. standard timer alternate function i/os standard timer functions number of alternate function i/os 100-pin package 64-pin package default mapping remapped tim 0 input capture 2 1 2 output compare/pwm 2 1 2 tim 1 input capture 2 1 1 output compare/pwm 2 1 1 tim 2 input capture 2 2 2 output compare/pwm 2 1 2 str750fxx str751fxx str752fxx str755fxx introduction 9/81 i2c bus the i2c bus interface can operate in multi-master and slave mode. it can support standard and fast modes (up to 400khz). high speed universal asynch. receiver transmitter (uart) the three uart interfaces are able to communicate at speeds of up to 2 mbit/s. they provide hardware management of the cts and rts signals and have lin master capability. to optimize the data transfer between the processor and the peripheral, two fifos (receive/transmit) of 16 bytes each have been implemented. one uart can be served by the dma controller (uart0). synchronous serial peripheral (ssp) the two ssps are able to communicate up to 8 mb it/s (ssp1) or up to 16 mbit/s (ssp0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 mbit/s as a slave device. to optimize the data transfer between the processor and the peripheral, two fifos (receive/transmit) of 8 x 16 bit words have been implemented. the ssps support the motorola spi or ti ssi protocols. one ssp can be served by the dma controller (ssp0). controller area network (can) the can is compliant with the specification 2.0 part b (active) with a bit rate up to 1mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. up to 32 message objects are handled through an internal ram buffer. in lqfp64 devices, can and usb cannot be connected simultaneously. universal serial bus (usb) the str750f embeds a usb device peripheral compatible with the usb full speed 12mbs. the usb interface implements a full speed (12 mbit/s) function interface. it has software configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock source is generated from the internal main pll. v dd must be in the range 3.3v10% for usb operation. adc (analog to digital converter) the 10-bit analog to digital converter, converts up to 16 external channels (11 channels in 64-pin devices) in single-shot or scan modes. in scan mode, continuous conversion is performed on a selected group of analog inputs. the minimum conversion time is 3.75 s (including the sampling time). the adc can be served by the dma controller. an analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. an irq is generated when the converted voltage is outside the programmed thresholds. the events generated by tim0, tim2 and pwm timers can be internally connected to the adc start trigger, injection trigger, and dma tr igger respectively, to allow the application to synchronize a/d conversion and timers. introduction str750fxx str751fxx str752fxx str755fxx 10/81 gpios (general purpose input/output) each of the 72 gpio pins (38 gpios in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. port 1.15 is an exception, it can be used as general-purpose input only or wake-up from standby mode (wkp_stdby). most of the gpio pins are shared with digital or analog alternate functions. str750fxx str751fxx str752fxx str755fxx introduction 11/81 3.2 block diagram figure 1. str750 block diagram p0[31:0] ext.it watchdog nested 10-bit adc jtag & ice-rt arm7tdmi-s 16af jtdi jtck jtms njtrst jtdo nrstin nrstout v 18 v dd_io 15af vdda_adc vssa_adc p1[19:0] apb bridge usb full speed usbdp usbdm mosi,miso, uart0 rx,tx,cts, serial memory sram 16kb rx,tx,cts, fifo 2x(16x8bit) uart1 fifo 2x(16x8bit) ssp1 fifo 2x(8x16bit) wakeup 4 cs as af gpio port 0 gpio port 1 60mhz v 18bkp mosi,miso, ssp0 fifo 2x(8x16bit) scl,sda i2c rx,tx,cts, uart2 fifo 2x(16x8bit) test gp dma 2xicap, 2xocmp 2xicap, 2xocmp 2xicap, 2xocmp xt1 xt2 rtc_xt1 rtc_xt2 pll apb (up to 32 mhz) v dda_pll v ssa_pll ck_usb ck_rtc as af as af as af as af rts as af rts as af as af as af as af flash 256kb dc-dc 3.3v to 1.8v v core v dd_io reset & power main v ss rtc as af arbiter pwm1, pwm1n pwm2, pwm2n pwm3, pwm3n pwm_emergency as af +16kb (rww) sclk, mosi miso as af 4 streams bus matrix ahb lite (up to 60mhz) cpu interface p2[19:0] gpio port 2 af: alternate function on i/o port pin note: i/os shown for 100 pin devices. 64-pin devices have the i/o set shown in figure 3 . can 2.0b rx,tx as af sck,nss sck,nss tb timer rts tim0 timer tim1 timer tim2 timer pwm timer ck_sys ahb ahb interrupt ctl osc 32xirq 2xfiq v backup v dda_adc v dda_pll low power hresetn presetn pclk hclk 4m osc 32k lp osc free osc clock manage- ment boot0 boot1, as af pin description str750fxx str751fxx str752fxx str755fxx 12/81 4 pin description figure 2. lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 adc_in13 / p1.12 adc_in0 / tim2_oc1/ p0.02 mco / tim0_ti1 / p0.01 boot0 / tim0_oc1 / p0.00 tim1_ti2 / p0.31 tim1_oc2 / p0.30 adc_in8 / tim1_ti1 / p0.29 tim1_oc1 / p0.28 test v ss_io adc_in6 / uart1_rts / p0.23 tim2_oc1/ p2.04 uart1_rts / p2.03 p2.02 adc_in5 / uart1_cts / p0.22 uart1_tx / p0.21 uart1_rx / p0.20 jtms / p1.19 jtck / p1.18 jtdo / p1.17 jtdi / p1.16 njtrst p2.01 p2.00 uart0_rts / rtck / p0.13 vreg_dis v ss_io v ssa_adc p2.10 p2.11 v dda_adc v dd_io p1.02 / tim2_oc2 p1.03 / tim2_ti2 usb_dp usb_dn p0.14 / can_rx p0.15 / can_tx p2.12 p2.13 p1.15 / wkp_stdby nrstin nrstout xrtc2 xrtc1 v 18bkp v ssbkp v ss18 v 18reg p2.14 smi_cs1 / adc_in2 / uart0_cts / p0.12 smi_cs2 / boot1 / uart0_tx / p0.11 smi_cs3 / uart0_rx / p0.10 i2c_sda / p0.09 i2c_scl / p0.08 p2.19 p2.18 uart2_rts / p2.17 adc_in12 / uart0_rts p1.11 adc_in7 /uart2_rts / p0.27 uart2_cts / p0.26 uart2_tx / p0.25 uart2_rx / p0.24 adc_in4 / ssp1_nss / usb_ck / p0.19 ssp1_mosi / p0.18 adc_in3 / ssp1_miso / p0.17 ssp1_sclk / p0.16 p2.16 v dd_io v dda_pll xt2 xt1 v ss_io v ssa_pll p2.15 p0.03 / tim2_ti1 / adc_in1 v dd_io v ss_io v ss18 v 18 p1.00 / tim0_oc2 p1.01 / tim0_ti2 p1.13 / adc_in14 p1.14/ adc_in15 p1.04 / pwm3n / adc_in9 p1.05 / pwm3 p1.06 / pwm2n/ adc_in10 p1.07 / pwm2 p1.08 / pwm1n/ adc_in11 p2.05 / pwm3n p2.06 / pwm3 p2.07 / pwm2n p2.08 / pwm2 p2.09 / pwm1n p1.09 / pwm1 p1.10 / pwm_emergency p0.04 / smi_cs0 / ssp0_nss p0.05 / ssp0_sclk / smi_ck p0.06 / smi_din / ssp0_miso p0.07 / smi_dout / ssp0_mosi lqfp100 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v 18bkp i/os = 16 a/d input channels = 15 external interrupts / wake-up lines str750fxx str751fxx str752fxx str755fxx pin description 13/81 figure 3. lqfp64 pinout i2c_scl / p0.08 adc_in12 / uart0_rts / p1.11 adc_in4 / ssp1_nss / usb_ck / p0.19 ssp1_mosi / p0.18 adc_in3 / ssp1_miso / p0.17 ssp1_sclk / p0.16 v dd_io_3 v dda_pll xt2 xt1 v ss_io_3 v ssa_pll smi_cs1 / adc_in2 / uart0_cts / uart2_rx /p0.12 smi_cs2 / boot1 / uart0_tx / p0.11 smi_cs3 / uart0_rx / p0.10 i2c_sda/ p0.09 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 adc_in8 / tim1_ti1 / p0.29 tim1_oc1 / p0.28 test v ss_io_4 uart1_tx / p0.21 uart1_rx / p0.20 jtms / p1.19 jtck / p1.18 jtdo / p1.17 jtdi / p1.16 njtrst uart2_tx / uart0_rts / rtck / p0.13 adc_in13 / p1.12 adc_in0 / tim2_oc1 / p0.02 mco / tim0_ti1 / p0.01 boot0 / tim0_oc1 / p0.00 v dd_io_2 p1.03 / tim2_ti2 p0.14 / can_rx or usb_dp p0.15 / can_tx or usb_dn nrstin nrstout xrtc2 xrtc1 v 18bkp v ssbkp v ss18 v 18reg v reg_dis v ss_io_2 v ssa_adc v dda_adc v 18 p1.04 / pwm3n / adc_in9 p1.05 / pwm3 p1.06 / pwm2n / adc_in10 p1.07 / pwm2 p1.08 / pwm1n / adc_in11 p1.09 / pwm1 p1.10 / pwm_emergency p0.04 / smi_cs0 /ssp0_nss p0.05 / ssp0_sclk / smi_ck p0.06 / smi_din / ssp0_miso p0.07 / smi_dout / ssp0_mosi p0.03 / tim2_ti1 / adc_in1 v dd_io_1 v ss_io_1 v ss18 lqfp64 = 11 a/d input channels = 13 external interrupts / wake-up lines v 18bkp i/os pin description str750fxx str751fxx str752fxx str755fxx 14/81 table 4. lfbga100 ball connections 123456 7 8 9 10 a p0.03 p1.13 p1.14 p1.04 p1.06 p1.08 p0.05 p0.06 p0.07 p1.02 b p1.12 p0.02 p0.01 p1.05 p1.07 p1.09 p0.04 p2.13 p1.03 p2.10 c p0.31 p0.00 v dd_io v 18 p1.10 p2.09 v ss_io v ssa_adc p2.11 usb_dp d p0.29 p0.30 v ss_io v ss18 p1.01 p1.15 v dd_io v dda_adc p2.12 usb_dn e p0.28 p0.23 p0.22 v ss_io test p1.00 nrstout vr eg_dis nrstin p0.14 f p2.03 p0.21 p0.20 p2.02 p2.04 p2.05 p2.06 v ss18 v ssbkp p0.15 g njtrst p1.18 p1.19 p2.01 p2.00 p2.07 2.08 v 18reg v 18bkp xrtc2 h p0.13 p1.16 p1.17 p2.19 p2.18 p 2.17 p0.24 p2.14 p2.16 xrtc1 j p0.11 p0.12 p1.11 p0.27 p0.19 p0.26 p0.25 p2.15 v dd_io v ss_io k p0.10 p0.09 p0.08 p0.18 p0.17 p0.16 xt1 xt2 v dda_pll v ssa_pll table 5. lfbga64 ball connections 1234 5 678 a p0.03 v ss_io p1.04 p1.06 p1.08 p0.05 p0.06 p0.07 b p1.12 v dd_io p1.05 p1.07 p1.09 p0.04 p1.10 p1.03 c p0.01 p0.02 p0.00 v 18 v ss18 v dd_io v ss_io p0.14 d p0.29 p0.28 test v ss_io vreg_dis v dda_adc v ssa_adc p0.15 e p1.18 p1.19 p0.20 p0.21 nrstout nrstin v 18bkp xrtc2 f p0.13 njtrst p1.16 p1.17 v 18reg v ss18 v ssbkp xrtc1 g p0.11 p0.12 p1.11 p0.19 v dd_io v ss_io v dda_pll v ssa_pll h p0.10 p0.09 p0.08 p0.17 p0.18 p0.16 xt2 xt1 str750fxx str751fxx str752fxx str755fxx pin description 15/81 4.0.1 pin description table legend / abbreviations for table 6 : type: i = input, o = output, s = supply, input levels: all inputs are lvttl at v dd_io = 3.3v+/-0.3v or ttl at v dd_io =5v 0.5v. in both cases, t t means v ilmax =0.8v v ihmin =2.0v inputs: all inputs can be configured as floating or with internal weak pull-up or pull down (pu/pd) outputs: all outputs can be configured as open drain (od) or push-pull (pp) (see also note 6 below ta bl e 6 ). there are 3 different types of output with different drives and speed characteristics: ?o8: f max = 40 mhz on c l =50pf and 8 ma static drive capability for v ol =0.4v and up to 20 ma for v ol =1.3v (see output driving current on page 55 ) ?o4: f max = 20 mhz on c l =50pf and 4 ma static drive capability for v ol =0.4v (see output driving current on page 55 ) ?o2: f max = 10 mhz on c l =50pf and 2 ma static drive capability of for v ol =0.4v (see output driving current on page 55 ) external interrupts/wake-up lines: eitx pin description str750fxx str751fxx str752fxx str755fxx 16/81 port reset state the reset state of the i/o ports is gpio input floating. exceptions are p1[19:16] and p0.13 which are configured as jtag alternate functions: the jtag inputs (jtdi, jtms and jtdi) are configured as input floating and are ready to accept jtag sequences. the jtag output jtdo is configured as floating when idle (no jtag operation) and is configured in output push-pull only when serial jtag data must be output. the jtag output rtck is always configured as output push-pull. it outputs '0' level during the reset phase and then outputs the jtck input signal resynchronized 3 times by the internal ahb clock. the gpio_pcx registers do not control jtag af selection, so the reset values of gpio_pcx for p1[19:16] and p0. 13 are the same as other ports. refer to the gpio section of the str750 reference manual for the register description and reset values. p0.11 and p0.00 are sampled by the boot logic after reset, prior to fetching the first word of user code at address 0000 0000h. when booting from smi (and only in this case), the reset state of the following gpios is "smi alternate function output enabled": ? p0.07 (smi_dout) ? p0.05 (smi_clk) ? p0.04 (smi_cs0) ? p0.06 (smi_din) note that the other smi pins: smi_cs1,2,3 (p0.12, p0.11, p0.10) are not affected. to avoid excess power consumption, unused i/o ports must be tied to ground. table 6. str750f pin description pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp 1b11b1 p1.12 / adc_in13 i/o t t x xeit12o8 x x port 1.12 adc: analog input 13 2b22c2 p0.02 / tim2_oc1 / adc_in0 i/o t t x xeit0o8 x x port 0.02 tim2: output compare 1 (4) adc: analog input 0 3b33c1 p0.01 / tim0_ti1 / mco i/o t t x xo8xx port 0.01 tim0: input capture / trigger / external clock 1 main clock output 4c24c3 p0.00 / tim0_oc1 / boot0 i/o t t x xo8xx port 0.00 / boot mode selection input 0 tim0: output compare 1 5 c1 p0.31 / tim1_ti2 i/o t t x xo2xx port 0.31 tim1: input capture / trigger / external clock 2 6d2 p0.30 / tim1_oc2 i/o t t x xo2xx port 0.30 tim1: output compare 2 str750fxx str751fxx str752fxx str755fxx pin description 17/81 7d15d1 p0.29 / tim1_ti1 / adc_in8 i/o t t x xo2xx port 0.29 tim1: input capture 1 adc: analog input 8 8e16d2 p0.28 / tim1_oc1 i/o t t x xo2xx port 0.28 tim1: output compare 1 9 e5 7 d3 test i reserved, must be tied to ground 10 e4 8 d4 vss_io s ground voltage for digital i/os 11 e2 p0.23 / uart1_rts / adc_in6 i/o t t x xo2xx port 0.23 uart1: ready to send output (4) adc analog input 6 12 f5 p2.04 / tim2_oc1 i/o t t x xo2xx port 2.04 tim2: output compare 1 (4) 13 f1 p2.03 / uart1_rts i/o t t x xo2xx port 2.03 uart1: ready to send output (4) 14 f4 p2.02 i/o t t x xo2xx port 2.02 15 e3 p0.22 / uart1_cts / adc_in5 i/o t t x xo2xx port 0.22 uart1: clear to send input adc: analog input 5 16 f2 9 e4 p0.21 / uart1_tx i/o t t x xo2xx port 0.21 uart1: transmit data output (remappable to p0.15) (4) 17 f3 10 e3 p0.20 / uart1_rx i/o t t x xo2xx port 0.20 uart1: receive data input (remappable to p0.14) (4) 18 g3 11 e2 p1.19 / jtms i/o t t xx o2 x x jtag mode selection input (6) por t 1.19 19 g2 12 e1 p1.18 / jtck i/o t t xx o2 x x jtag clock input (6) por t 1.18 20 h3 13 f4 p1.17 / jtdo i/o t t xx o8 x x jtag data output (6) por t 1.17 21 h2 14 f3 p1.16 / jtdi i/o t t xx o2 x x jtag data input (6) por t 1.16 22 g1 15 f2 njtrst i t t jtag reset input (5) 23 g4 p2.01 i/o t t x xo2xx port 2.01 24 g5 p2.00 i/o t t x xo2xx port 2.00 25 h1 16 f1 p0.13 / rtck / uart0_rts uart2_tx i/o t t xx o8 x x jtag return clock output (6) por t 0.13 uart0: ready to send output (4) uart2: transmit data output (when remapped) (8) table 6. str750f pin description (continued) pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp pin description str750fxx str751fxx str752fxx str755fxx 18/81 26 j2 17 g2 p0.12 / uart2_rx / uart0_cts / adc_in2 / smi_cs1 i/o t t x xo4xx port 0.12 uart0: clear to send input adc: analog input 2 serial memory interface: chip select output 1 uart2: receive data input (when remapped) (8) 27 j1 18 g1 p0.11 / uart0_tx / boot1 / smi_cs2 i/o t t x xo4xx port 0.11/boot mode selection input 1 uart0: transmit data output serial memory interface: chip select output 2 28 k1 19 h1 p0.10 / uart0_rx / smi_cs3 i/o t t x xeit4o2 x x port 0.10 uart0: receive data input serial memory interface: chip select output 3 29 k2 20 h2 p0.09 / i2c_sda i/o t t x xo4xx port 0.09 i2c: serial data 30 k3 21 h3 p0.08 / i2c_scl i/o t t x xeit3o4 x x port 0.08 i2c: serial clock 31 h4 p2.19 i/o t t x xo2xx port 2.19 32 h5 p2.18 i/o t t x xo2xx port 2.18 33 h6 p2.17 / uart2_rts i/o t t x xo2xx port 2.17 uart2: ready to send output (4) 34 j3 22 g3 p1.11 /uart0_rts adc_in12 i/o t t x xeit11o8 x x port 1.11 uart0: ready to send output (4) adc: analog input 12 35 j4 p0.27 / uart2_rts / adc_in7 i/o t t x xo2xx port 0.27 uart2: ready to send output (8) adc: analog input 7 36 j6 p0.26 / uart2_cts i/o t t x xo2xx port 0.26 uart2: clear to send input 37 j7 p0.25 / uart2_tx i/o t t x xo2xx port 0.25 uart2: transmit data output (remappable to p0.13) (8) 38 h7 p0.24 / uart2_rx i/o t t x xo2xx port 0.24 uart2: receive data input (remappable to p0.12) (8) 39 j5 23 g4 p0.19 / usb_ck / ssp1_nss / adc_in4 i/o t t x xeit6o2 x x port 0.19 ssp1: slave select input (remappable to p0.11) (8) adc: analog input 4 usb: 48 mhz clock input 40 k4 24 h5 p0.18 / ssp1_mosi i/o t t x xo2xx port 0.18 ssp1: master out/slave in data (remappable to p0.10) (8) 41 k5 25 h4 p0.17 / ssp1_miso / adc_in3 i/o t t x xo2xx port 0.17 ssp1: master in/slave out data (remappable to p0.09) (8) adc: analog input 3 42 k6 26 h6 p0.16 / ssp1_sclk i/o t t x xo2xx port 0.16 ssp1: serial clock (remappable to p0.08) (8) table 6. str750f pin description (continued) pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp str750fxx str751fxx str752fxx str755fxx pin description 19/81 43 h9 p2.16 i/o t t x xo2xx port 2.16 44 j9 27 g5 vdd_io s supply voltage for digital i/os 45 k9 28 g7 vdda_pll s supply voltage for pll 46 k8 29 h7 xt2 4 mhz main oscillator 47 k7 30 h8 xt1 48 j10 31 g6 vss_io s ground voltage for digital i/os 49 k10 32 g8 vssa_pll s ground voltage for pll 50 j8 p2.15 i/o t t x xo2xx port 2.15 51 h8 p2.14 i/o t t x xo2xx port 2.14 52 g8 33 f5 v18reg s stabilization for main voltage regulator. requires external capacitors of at least 10f between v18reg and vss18. see figure 4 . to be connected to the 1.8v external power supply when embedded regulators are not used, 53 f8 34 f6 vss18 s ground voltage for the main voltage regulator 54 f9 35 f7 vssbkp s stabilization for low power voltage regulator. 55 g9 36 e7 v18bkp s ground voltage for the low power voltage regulator. requires external capacitors of at least 1f between v18bkp and vssbkp. see figure 4 . to be connected to the 1.8v external power supply when embedded regulators are not used, 56 h10 37 f8 xrtc1 x 32 khz oscillator for realtime clock 57 g10 38 e8 xrtc2 x 58 e7 39 e5 nrstout o x reset output 59 e9 40 e6 nrstin i t t x reset input 60 d6 p1.15 / wkp_stdby it t x eit15 x port 1.15 wake-up from standby input pin 61 b8 p2.13 i/o t t x xo2xx port 2.13 62 d9 p2.12 i/o t t x xo2xx port 2.12 63 f10 41 (7) d8 (7) p0.15 / can_tx i/o t t x xo2xx port 0.15 can: transmit data output 64 e10 42 (7) c8 (7) p0.14 / can_rx i/o t t x xeit5o2 x x port 0.14 can: receive data input 65 d10 41 (7) d8 (7) usb_dn i/o usb: bidirectional data (data -) 66 c10 42 (7) c8 (7) usb_dp i/o usb: bidirectional data (data +) 67 b9 43 b8 p1.03 / tim2_ti2 i/o t t x xo2xx port 1.03 tim2: input capture / trigger / external clock 2 (remappable to p0.07) (8) table 6. str750f pin description (continued) pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp pin description str750fxx str751fxx str752fxx str755fxx 20/81 68 a10 p1.02 / tim2_oc2 i/o t t x xo2xx port 1.02 tim2: output compare 2 (remappable to p0.06) (8) 69 d7 44 c6 vdd_io s supply voltage for digital i/os 70 d8 45 d6 vdda_adc s supply voltage for a/d converter 71 c9 p2.11 i/o t t x xo2xx port 2.11 72 b10 p2.10 i/o t t x xo2xx port 2.10 73 c8 46 d7 vssa_adc s ground voltage for a/d converter 74 c7 47 c7 vss_io s ground voltage for digital i/os 75 e8 48 d5 vreg_dis i t t voltage regulator disable input 76 a9 49 a8 p0.07 / smi_dout / ssp0_mosi i/o t t x xeit2o4 x x port 0.07 serial memory interface: data output ssp0: master out slave in data 77 a8 50 a7 p0.06 / smi_din / ssp0_miso i/o t t x xo4xx port 0.06 serial memory interface: data input ssp0: master in slave out data 78 a7 51 a6 p0.05 / ssp0_sclk / smi_ck i/o t t x xeit1o4 x x port 0.05 ssp0: serial clock serial memory interface: serial clock output 79 b7 52 b6 p0.04 / smi_cs0 / ssp0_nss i/o t t x xo4xx port 0.04 serial memory interface: chip select output 0 ssp0: slave select input 80 c5 53 b7 p1.10 pwm_emerge ncy i/o t t x xeit10o2 x x port 1.10 pwm: emergency input 81 b6 54 b5 p1.09 / pwm1 i/o t t x xeit9o4 x x port 1.09 pwm: pwm1 output 82 c6 p2.09 / pwm1n i/o t t x xo2xx port 2.09 pwm: pwm1 complementary output (4) 83 g7 p2.08 / pwm2 i/o t t x xo2xx port 2.08 pwm: pwm2 output (4) 84 g6 p2.07 / pwm2n i/o t t x xo2xx port 2.07 pwm: pwm2 complementary output (4) 85 f7 p2.06 / pwm3 i/o t t x xo2xx port 2.06 pwm: pwm3 output (4) 86 f6 p2.05 / pwm3n i/o t t x xo2xx port 2.05 pwm: pwm3 complementary output (4) 87 a6 55 a5 p1.08 / pwm1n / adc_in11 i/o t t x xo4xx port 1.08 pwm: pwm1 complementary output (8) adc: analog input 11 88 b5 56 b4 p1.07 / pwm2 i/o t t x xeit8o4 x x port 1.07 pwm: pwm2 output (4) 89 a5 57 a4 p1.06 / pwm2n / adc_in10 i/o t t x xo4xx port 1.06 pwm: pwm2 complementary output (4) adc: analog input 10 90 b4 58 b3 p1.05 / pwm3 i/o t t x xeit7o4 x x port 1.05 pwm: pwm3 output (4) table 6. str750f pin description (continued) pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp str750fxx str751fxx str752fxx str755fxx pin description 21/81 91 a4 59 a3 p1.04 / pwm3n / adc_in9 i/o t t x xo4xx port 1.04 pwm: pwm3 complementary output (4) adc: analog input 9 92 a3 p1.14 / adc_in15 i/o t t x xo8xx port 1.14 adc: analog input 15 93 a2 p1.13 / adc_in14 i/o t t x xeit13o8 x x port 1.13 adc: analog input 14 94 d5 p1.01 / tim0_ti2 i/o t t x xo2xx port 1.01 tim0: input capture / trigger / external clock 2 (remappable to p0.05) (8) 95 e6 p1.00 / tim0_oc2 i/o t t x xo2xx port 1.00 tim0: output compare 2 (remappable to p0.04) (8) 96 c4 60 c4 v18 s stabilization for main voltage regulator. requires external capacitors 33nf between v18 and vss18. see figure 4 . to be connected to the 1.8v external power supply when embedded regulators are not used. 97 d4 61 c5 vss18 s ground voltage for the main voltage regulator. 98 d3 62 a2 vss_io s ground voltage for digital i/os 99 c3 63 b2 vdd_io s supply voltage for digital i/os 100 a1 64 a1 p0.03 / tim2_ti1 / adc_in1 i/o t t x xo2xx port 0.03 tim2: input capture / trigger / external clock 1 adc: analog input 1 1. for str755fvx part numbers, the usb pins must be left unconnected. 2. the non available pins on lqpfp64 and lfbga64 packages are internally tied to low level. 3. none of the i/os are true open drain: when configured as open drain, there is always a protection diode between the i/o pin and vdd_io. 4. in the 100-pin package, this alternate function is duplicated on two ports. you can configure one port to use this af, the other port is then free for general purpose i/o (gpio), external in terrupt/wake-up lines, or analog input (adc_in) where these functions are listed in the table. 5. it is mandatory that the njtrst pin is reset to ground duri ng the power-up phase. it is recommended to connect this pin to nrstout pin (if avai lable) or nrstin. 6. after reset, these pins are enabled as jtag alternate function see ( port reset state on page 16 ). to use these ports as general purpose i/o (gpio), the db goff control bit in the gpio_remap0r regist er must be set by software (in this case, debugging these i/os via jt ag is not possible). 7. there are two different tqfp and bg a 64-pin packages: in the first one, pins 41 and 42 are mapped to usb dn/dp while for the second one, they are mapped to p0.15/can_tx and p0.14/can_rx. 8. for details on remapping these alternate functions , refer to the gpio_remap0r register description. table 6. str750f pin description (continued) pin n pin name type input output usable in standby main function (after reset) alternate function lqfp100 (1) lfbga100 (1) lqfp64 (2) lfbga64 (2) input level floating pu/pd ext. int /wake-up capability od (3) pp pin description str750fxx str751fxx str752fxx str755fxx 22/81 figure 4. required external capacitors when regulators are used lqfp100 lqfp64 52 60 96 33 nf 53 10 f 33 nf 54 55 1f 61 v 18 v 18reg v 18 v 18bkp 97 v ss18 v ssbkp 44 v dd_io 1 f v ss18 v ss18 33 34 10 f 35 36 1f v 18reg v 18bkp v ss18 v ssbkp 27 v dd_io 1 f lfbga100 g8 c4 33 nf f8 10 f f9 g9 1f v 18reg v 18 v 18bkp d4 v ss18 v ssbkp j9 v dd_io 1 f v ss18 lfbga64 c4 33 nf c5 v 18 v ss18 f5 f6 10 f f7 e7 1f v 18reg v 18bkp v ss18 v ssbkp g5 v dd_io 1 f str750fxx str751fxx str752fxx str755fxx pin description 23/81 4.1 memory map figure 5. memory map reserved addressable memory space 0 1 2 3 4 1k 5 6 7 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 0xffff 8000 0xffff 83ff 0xffff 8400 0xffff 87ff 0xffff 8800 0xffff 8bff 0xffff 8c00 0xffff 8fff 0xffff 9000 0xffff 93ff 0xffff 9400 0xffff 97ff 0xffff 9800 0xffff 9bff 0xffff 9c00 0xffff 9fff 0xffff a000 0xffff a3ff 0xffff a800 0xffff abff 0xffff ac00 0xffff afff 0xffff b000 0xffff c3ff 0xffff c400 0xffff c7ff 0xffff c800 0xffff cbff 0xffff cc00 0xffff d000 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 0x6000 0047 0x0000 0000 peripheral memory space 4 gbytes 32 kbytes boot memory (1) 128k/256k conf + mrcc 1k apb to arm7 bridge 0xffff 8000 32k reserved 0xffff cfff internal sram 16k 0x4000 3fff smi ext. memory 0x83ff ffff 4 x 16m 0xffff c000 0xffff d400 0xffff d3ff 0xffff d800 0xffff d7ff 0xffff dc00 0xffff dbff 0xffff e000 0xffff dfff 0xffff e400 0xffff e3ff 0xffff e800 0xffff e7ff 0xffff ec00 0xffff ebff 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k adc tim0 tim1 tim2 pwm usb registers can reserved i2c reserved uart0 uart1 uart2 reserved rtc eic 0xffff f800 0xffff f7ff 0xffff f400 0xffff f3ff 0xffff f000 0xffff efff 0xffff b3ff 0xffff b400 0xffff b7ff 0xffff b800 1k 0xffff bbff gpio i/o ports reserved dma wdg reserved ssp0 ssp1 1k 0xffff bfff 0xffff bc00 tb timer reserved flash memory space 128/256 kbytes b0f5 0x2000 1fff 0x2000 0000 0x2000 2000 0x2000 3fff 0x2000 4000 0x2000 5fff 0x2000 6000 0x2000 7fff 0x2000 8000 0x2000 ffff 0x2001 0000 0x2001 ffff 0x2010 0000 0x2010 0017 0x2010 c000 0x2010 dfff 8k 8k 8k 8k 32k 24b 64k b0f4 flash registers internal flash 128k/256k+16k+32b b0f6 (2) 0x2002 0000 0x2002 ffff 64k b0f7 (2) 0x2003 0000 0x2003 ffff 64k reserved 0xffff a200 extit 0x2010 0017 b0f3 b0f2 b0f1 b0f0 1k 1k 1k 0xffff a400 0xffff a7ff 1k (1) in internal flash boot mode, internal flash is aliased at 0x0000 0000h (2) only available in str750fx2 8k systemmemory 0x200c 0000 0x200c 1fff 8k b1f1 0x200c 2000 8k usb ram 256 x16-bit reserved reserved 0x9000 0000 0x9000 0013 smi registers 20b b1f0 0x200c 3fff 0x200c 4000 0xffff ffff 0xffff fc00 0xffff fbff 1k reserved electrical parameters str750fxx str751fxx str752fxx str755fxx 24/81 5 electrical parameters 5.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a max (given by the selected temperature range). data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd_io =3.3 v (for the 3.0 v v dd_io 3.6 v voltage range) and v 18 =1.8 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. str750fxx str751fxx str752fxx str755fxx electrical parameters 25/81 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 6 . figure 6. pin loading conditions 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 7 . figure 7. pin input voltage c l =50pf str7 pin v in str7 pin electrical parameters str750fxx str751fxx str752fxx str755fxx 26/81 5.1.6 power supply schemes when mentioned, some electrical paramete rs can refer to a dedicated power scheme among the four possibilities. the four di fferent power schemes are described below. power supply scheme 1: single external 3.3 v power source figure 8. power supply scheme 1 3.3v main voltage gp i/os out adc adc in kernel logic backup in v 18_bkp (cpu & digital & +/-0.3v v io =3.3v v dd_adc v ss_adc pll 3.3v 3.3v v ss_pll v ss_io v dd_io v 18reg v dd_pll v ss18 v ss_bkp osc32k, rtc regulator memories) circuitry wakeup logic, vreg_dis backup registers) i/o logic in standby mode this block is kept powered on normal power switch mode v 18 10f 33nf 1f 1f low power voltage regulator v backup v core v 18 v lpvreg ~1.4v v mvreg = 1.8v v ss18 str750fxx str751fxx str752fxx str755fxx electrical parameters 27/81 power supply scheme 2: dual external 1.8v and 3.3v supply figure 9. power supply scheme 2 3.3v main voltage gp i/os out adc adc in in v 18_bkp +/-0.3v v io =3.3v v dd_adc v ss_adc pll 3.3v 3.3v v ss_pll v ss_io v dd_io v 18reg v dd_pll v ss_bkp regulator vreg_dis off 1.8v v ss18 i/o logic off kernel backup (core & digital & (osc32k, rtc memories) circuitry wakeup logic, backup registers) v dd_io power switch v core v backup v 18 low power voltage regulator note : the external 3.3 v power supply must always be kept on v lpvreg v mvreg electrical parameters str750fxx str751fxx str752fxx str755fxx 28/81 power supply scheme 3: single external 5 v power source figure 10. power supply scheme 3 5.0v main voltage gp i/os out adc adc in kernel logic backup in v 18_bkp (cpu & digital & +/-0.5v v io =5.0v v dd_adc v ss_adc pll 5.0v 5.0v v ss_pll v ss_io v dd_io v 18reg v dd_pll v ss18 v ss_bkp osc32k, rtc regulator memories) circuitry wakeup logic, vreg_dis backup registers) i/o logic in standby mode this block is kept powered on normal power switch mode v 18 10f 33nf 1f 1f low power voltage regulator v backup v core v 18 v lpvreg ~1.4v v mvreg = 1.8v v ss18 str750fxx str751fxx str752fxx str755fxx electrical parameters 29/81 power supply scheme 4: dual external 1.8 v and 5.0 v supply figure 11. power supply scheme 4 5.1.7 i/o characteristics versus the va rious power schemes (3.3v or 5.0v) unless otherwise mentione d, all the i/o characteristics are valid for both v dd_io =3.0 v to 3.6 v with bit en33=1 v dd_io =4.5 v to 5.5 v with bit en33=0 when v dd_io =3.0 v to 3.6 v, i/os are not 5v tolerant. 5.1.8 current consum ption measurements all the current consumption measurements mentioned below refer to power scheme 1 and 2 as described in figure 12 and figure 13 5.0v main voltage low power voltage gp i/os out adc adc in in +/-0.5v v io =5.0v v dd_adc v ss_adc pll 5.0v 5.0v v ss_pll v ss_io v dd_io v dd_pll regulator off i/o logic off kernel backup (core & digital & (osc32k, rtc memories) circuitry wakeup logic, backup registers) power switch v core v backup v 18_bkp v 18reg v ss_bkp vreg_dis 1.8v v ss18 v dd_io v 18 regulator note : the external 5.0v power supply must always be kept on v lpvreg v mvreg electrical parameters str750fxx str751fxx str752fxx str755fxx 30/81 figure 12. power consumption measurements in power scheme 1 (regulators enabled) figure 13. power consumption measurements in power scheme 2 (regulators disabled) v dd_io pins v 18 pins (including v 18bkp ) i dd 3.3v supply ballast regulator transistor 3.3v internal load 1.8v internal load i dd is measured, which corresponds to the total current consumption : i 33 i 18 i dd = i dda_pll + i dda_adc + i 33 + i 18 v dda_pll pins pll load i dda_pll adc load i dda_adc v dda_adc pins v dd_io pins v 18 pins (including v 18bkp ) i dd_v33 3.3v supply 3.3v internal load 1.8v internal load i 33 i 18 v dda_pll pins pll load i dda_pll adc load i dda_adc v dda_adc pins i dd_v18 1.8v supply i dd_v33 and i dd_v18 are measured which correspond to: i dd_v33 = i dda_pll + i dda_adc + i 33 i dd_v18 = i 18 str750fxx str751fxx str752fxx str755fxx electrical parameters 31/81 figure 14. power consumption measurements in power scheme 3 (regulators enabled) figure 15. power consumption measurements in power scheme 4 (regulators disabled) v dd_io pins v 18 pins (including v 18bkp ) i dd 5.0v supply ballast regulator transistor 5.0v internal load 1.8v internal load i dd is measured, which corresponds to the total current consumption : i 50 i 18 i dd = i dda_pll + i dda_adc + i 50 + i 18 v dda_pll pins pll load i dda_pll adc load i dda_adc v dda_adc pins v dd_io pins v 18 pins (including v 18bkp ) i dd_v50 5.0v supply 5.0v internal load 1.8v internal load i 50 i 18 v dda_pll pins pll load i dda_pll adc load i dda_adc v dda_adc pins i dd_v18 1.8v supply i dd_v50 and i dd_v18 are measured which correspond to: i dd_v50 = i dda_pll + i dda_adc + i 50 i dd_v18 = i 18 electrical parameters str750fxx str751fxx str752fxx str755fxx 32/81 5.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 5.2.1 voltage characteristics table 7. voltage characteristics symbol ratings min max unit v dd_x - v ss_x (1) 1. all 3.3 v or 5.0 v power (v dd_io , v dda_adc , v dda_pll ) and ground (v ss_io , v ssa_adc , v dda_adc ) pins must always be connected to the ex ternal 3.3v or 5.0v supply. w hen powered by 3.3v, i/os are not 5v tolerant. including v dda_adc and v dda_pll -0.3 6.5 v v 18 - v ss18 digital 1.8 v supply voltage on all v 18 power pins (when 1.8 v is provided externally) -0.3 2.0 v in input voltage on any pin (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in str750fxx str751fxx str752fxx str755fxx electrical parameters 35/81 5.3.3 embedded voltage regulators subject to general operating conditions for v dd_io , and t a table 12. embedded voltage regulators symbol parameter conditions min typ max unit v mvreg mvreg power supply (1) 1. v mvreg is observed on the v 18 , v 18reg and v 18bkp pins except in the following case: - in stop mode with mvreg off (lp_param13 bit). see note 2. - in standby mo de. see note 2. load <150 ma 1.65 1.80 1.95 v v lpvreg lpvreg power supply (2) 2. in standby mode, v lpvreg is observed on the v 18bkp pin in stop mode, v lpvreg is observed on the v 18 , v 18reg and v 18bkp pins. load <10 ma 1.30 1.40 1.50 v t vreg_pwrup (1) voltage regulators start-up time (to reach 90% of final v 18 value) at v dd_io power-up (3) 3. once v dd_io has reached 3.0 v, the rsm (regulator star tup monitor) generates an internal reset during this start-up time. v dd_io rise slope = 20 s/v 80 s v dd_io rise slope = 20 ms/v 35 ms electrical parameters str750fxx str751fxx str752fxx str755fxx 36/81 5.3.4 supply current characteristics the current consumption is measured as described in figure 12 on page 30 and figure 13 on page 30 . subject to general operating conditions for v dd_io , and t a maximum power consumption for the measurements in ta b l e 1 3 and ta b l e 1 4 , the mcu is placed under the following conditions: all i/o pins are configured in output push-pull 0 all peripherals are disabled exce pt if explicitly mentioned. embedded regulators are used to provide 1.8 v (except if explicitly mentioned). table 13. maximum power consumption in run and wfi modes symbol parameter conditions (1) 1. the conditions for these consumption measurements are described at the beginning of section 5.3.4 . typ (2) 2. typical data are based on t a =25c, v dd_io =3.3v or 5.0v and v 18 =1.8v unless otherwise specified. max (3) 3. data based on product characterisation, tested in production at v dd_io max and v 18 max (1.95v in dual supply mode or regulator output va lue in single supply mode) and t a max. unit i dd supply current in run mode external clock with pll multiplication, code running from ram, all peripherals enabled in the mrcc_plcken register: f hclk =60 mhz, f pclk =30 mhz single supply scheme see figure 12 / figure 14 3.3v and 5v range 80 90 ma supply current in wfi mode external clock, code running from ram: f hclk =60 mhz, f pclk =30 mhz single supply scheme see figure 12 ./ figure 14 parameter setting burst=1, wfi_flashen=1 3.3v and 5v range 62 67 ma str750fxx str751fxx str752fxx str755fxx electrical parameters 37/81 table 14. maximum power consumpt ion in stop and standby modes symbol parameter conditions (1) typ (2) max (3) unit t a 25c t a 85c t a 105c i dd supply current in stop mode lp_param bits: all off (4) single supply scheme see figure 12 . 3.3v range 12 16 117 250 a lp_param bits: all off dual supply scheme see figure 13 . i dd_v18 i dd_v33 5 <1 8 3 60 20 110 26 a lp_param bits: all off (4) single supply scheme see figure 10 5v range 15 22 160 310 a lp_param bits: all off dual supply scheme see figure 11 i dd_v18 i dd_v50 5 3 8 6 60 50 110 65 a supply current in standby mode rtc off 3.3 v range 10 20 25 28 5v range 15 25 30 33 1. the conditions for these consumption m easurements are described at the beginning of section 5.3.4 . 2. typical data are based on t a =25c, v dd_io =3.3v or 5.0v and v 18 =1.8v unless otherwise specified. 3. data based on product characteri sation, tested in production at v dd_io max and v 18 max (1.95v in dual supply mode or regulator output value in single supply mode). 4. in this mode, the whole digital circuitr y is powered internally by the lpvreg at approximately 1.4v, which significantly reduces the leakage currents. electrical parameters str750fxx str751fxx str752fxx str755fxx 38/81 figure 16. power consumption in stop mode in single supply scheme (3.3 v range) figure 17. power consumption in stop mode single supply scheme (5 v range) 0 50 100 150 200 250 300 -402545557595105 temp (c) istop (ua) typ (3. 3v) max (3.6v) 0 50 100 150 200 250 300 350 -402545557595105 temp (c) istop (ua) typ (5.0v) max (5.5v) figure 18. power consumption in standby mode (3.3 v range) figure 19. power consumption in standby mode (5 v range) 0 5 10 15 20 25 30 -40 25 105 temp (c) istandby (ua) typ (3.3v) max (3.6v) 0 5 10 15 20 25 30 35 -40 25 105 temp (c) istandby (ua) typ (5.0v) max (5.5v) str750fxx str751fxx str752fxx str755fxx electrical parameters 39/81 typical power consumption the following measurement conditions apply to ta bl e 1 5 , ta b l e 1 6 and ta bl e 1 7 . in run mode: program is executed from flash (except if especially mentioned). the program consists of an infinite loop. when f hclk > 32 mhz, burst mode is activated. a standard 4 mhz crystal source is used. in all cases the pll is used to multiply the frequency. all measurements are done in the single supply scheme with internal regulators used (see figure 12 ) in wfi mode: in wfi mode the measurement conditions are similar to run mode (osc4m and pll enabled). in addition, the flash can be disabled depending on burst mode activation: ? for ahb frequencies greater than 32 mhz, burst mode is activated and the flash is kept enabled by setting the wfi_flash_en bit (this bit cannot be reset when burst mode is activated). ? for ahb frequencies less than or equal to 32 mhz, burst mode is deactivated, wfi_flash_en is reset and the lp_param14 bit is set (flash is disabled in wfi mode). in slow mode: the same program as in run mode is executed from flash. the cpu is clocked by the freeosc, osc4m, lposc or osc32k. only extit peripheral is enabled in the mrcc_pclken register. in slow-wfi mode: in slow-wfi, the measurement conditions are similar to slow mode (cpu clocked by a low frequency clock). in addition, the lp_param14 bit is set (flash is off). the wfi routine itself is executed from sram (it is not allowed to execute a wfi from the internal flash) in stop mode: several measurements are given: in the sing le supply scheme with internal regulators used (see figure 12 ): and in the dual supply scheme (see figure 13 ). in standby mode: three measurements are given: ? the rtc is disabled, only the consumption of the lpvreg and rsm remain (almost no leakage currents) ? the rtc is running, clocked by a standard 32.768 khz crystal. ? the rtc is running, clocked by the internal low power rc oscillator (lposc) standby mode is only supported in the single supply scheme (see figure 12 ) electrical parameters str750fxx str751fxx str752fxx str755fxx 40/81 subject to general operating conditions for v dd_io , and t a table 15. single supply typical power consumpti on in run, wfi, slow and slow-wfi modes symbol para meter conditions 3.3v typ (1) 5v typ (2) unit i dd (3) supply current in run mode (4) clocked by osc4m with pll multiplication, all peripherals enabled in the mrcc_plcken register: f hclk =60 mhz, f pclk =30 mhz f hclk =56 mhz, f pclk =28 mhz f hclk =48 mhz, f pclk =24 mhz f hclk =32 mhz, f pclk =32 mhz f hclk =16 mhz, f pclk =16 mhz f hclk =8 mhz, f pclk =8 mhz 80 75 65 59 34 20 82 77 67 61 37 22 ma clocked by osc4m with pll mu ltiplication, only extit peripheral enabled in the mrcc_plcken register: f hclk =60 mhz, f pclk =30 mhz f hclk =56 mhz, f pclk =28 mhz f hclk =48 mhz, f pclk =24 mhz f hclk =32 mhz, f pclk =32 mhz f hclk =16 mhz, f pclk =16 mhz f hclk =8 mhz, f pclk =8 mhz 65 60 54 42 22 16 67 62 55 44 24 18 ma supply current in wfi mode (4) clocked by osc4m with pll mu ltiplication, only extit peripheral enabled in the mrcc_plcken register: f hclk =60 mhz, f pclk =30 mhz (5) f hclk =56 mhz, f pclk =28 mhz (5) f hclk =48 mhz, f pclk =24 mhz (5) f hclk =32 mhz, f pclk =32 mhz (6) f hclk =16 mhz, f pclk = 16 mhz (6) f hclk = 8 mhz, f pclk = 8 mhz (6) 62 59 53 22 13 10 63 60 54 23 15 11 ma supply current in slow mode (4) clocked by freeosc: f hclk =f pclk =~5 mhz, clocked by osc4m: f hclk =f pclk =4 mhz clocked by lposc: f hclk =f pclk =~300 khz clocked by osc32k: f hclk =f pclk =32.768 khz 9 8 3.65 3.5 10 9 3.9 4.2 ma supply current in slow-wfi mode (4)(7) clocked by freeosc: f hclk =f pclk =~5 mhz clocked by osc4m: f hclk =f pclk =4 mhz clocked by lposc: f hclk =f pclk =~300 khz clocked by osc32k: f hclk =f pclk =32.768 khz 3.5 3.1 1.15 0.98 4.0 3.75 1.65 1.5 ma 1. typical data based on t a =25 c and v dd_io =3.3v. 2. typical data based on t a =25 c and v dd_io =5.0v. 3. the conditions for these consumption m easurements are described at the beginning of section 5.3.4 on page 36 . 4. single supply scheme see figure 14 . 5. parameter setting burst=1, wfi_flashen=1 6. parameter setting burst=0, wfi_flashen=0 7. parameter setting wfi_flashen=0, osc4moff=1 str750fxx str751fxx str752fxx str755fxx electrical parameters 41/81 subject to general operating conditions for v dd_io , and t a table 16. dual supply supply typical power consumption in run, wfi, slow and slow-wfi modes to calculate the power consumption in dual supply mode, refer to the values given in ta bl e 1 5 . and consider that this consumption is split as follows: i dd(single supply) ~i dd(dual supply) = i dd_v18 + i dd(vdd_io) for 3.3v range: i dd(vdd_io) ~ 1 to 2 ma for 5v range: i dd(vdd_io) ~ 2 to 3 ma therefore most of the consumption is sunk on the v 18 power supply this formula does not apply in stop and standby modes, refer to ta b l e 1 7 . table 17. typical powe r consumption in stop and standby modes symbol parameter conditions 3.3v typ (1) 5v typ (2) unit i dd (3) supply current in stop mode (4) lp_param bits: all off (5) 12 15 a lp_param bits : mvreg on, osc4m off, flash off (6) 130 135 lp_param bits: mvreg on, osc4m on , flash off (6) 1950 1930 lp_param bits: mvreg on, osc4m off, flash on (6) 630 635 lp_param bits: mvreg on, osc4m on, flash on (6) 2435 2425 supply current in stop mode (7) lpparam bits: all off, with v 18 =1.8 v i dd_v18 i dd_v33 5 <1 5 <1 a lp_param bits: osc4m on, flash off i dd_v18 i dd_v33 410 1475 410 1435 lp_param bits: osc4m off, flash on i dd_v18 i dd_v33 550 <1 550 1 lp_param bits: osc4m on, flash on i dd_v18 i dd_v33 910 1475 910 1445 supply current in standby mode (4) rtc off 11 14 a rtc on clocked by osc32k 14 18 1. typical data are based on t a =25c, v dd_io =3.3 v and v 18 =1.8 v unless otherwise indicated in the table. 2. typical data are based on t a =25c, v dd_io =5.0 v and v 18 =1.8 v unless otherwise indicated in the table. 3. the conditions for these consumption m easurements are described at the beginning of section 5.3.4 on page 36 . 4. single supply scheme see figure 12 . 5. in this mode, the whole digital circuitr y is powered internally by the lpvreg at approximately 1.4 v, which significantly reduces the leakage currents. 6. in this mode, the whole digital circuitry is powered internally by the mvreg at 1.8 v. 7. dual supply scheme see figure 13 . electrical parameters str750fxx str751fxx str752fxx str755fxx 42/81 supply and clock manager power consumption table 18. supply and clock manager power consumption symbol parameter conditions (1) 3.3v typ 5v typ unit i dd(osc4m) supply current of resonator oscillator in stop or wfi mode (lp_param bit: osc4m on) external components specified in : 4/8 mhz crystal / ceramic resonator oscillator (xt1/xt2) on page 46 1815 1795 a i dd(flash) flash static current consumption in stop or wfi mode (lp_param bit flash on) 515 515 i dd(mvreg) main voltage regulator static current consumption in stop mode (lp_param bit: mvreg on) 130 135 i dd(lpvreg) low power voltage regulator + rsm current static current consumption stop mode includes leakage where v 18 is internally set to 1.4 v 12 15 standby mode where v 18bkp and v 18 are internally set to 1.4 v and 0 v respectively 11 14 1. measurements performed in 3.3v single supply mode see figure 12 str750fxx str751fxx str752fxx str755fxx electrical parameters 43/81 on-chip peripheral power consumption conditions: ?v dd_io =v dda_adc =v dda_pll =3.3 v or 5 v 10% unless otherwise specified. ?t a = 25 c ? clocked by osc4m with pll multiplication, f ck_sys =64 mhz, f hclk =32 mhz, f pclk =32 mhz . table 19. on-chip peripherals symbol parameter typ (3.3v and 5.0v) unit i dd(tim) tim timer supply current (1) 1. data based on a differential i dd measurement between reset configur ation and timer counter running at 32 mhz. no ic/oc programmed (no i/o pads toggling) 0.7 ma i dd(pwm) pwm timer supply current (2) 2. data based on a differential i dd measurement between reset configuration and pwm running at 32 mhz. this measurement does not incl ude pwm pads toggling consumption. 1 i dd(ssp) ssp supply current (3) 3. data based on a differential i dd measurement between reset configuration and permanent spi master communication at maximum speed 16 mhz. the data sent is 55h. this measurement does not include the pad toggling consumption. 1.3 i dd(uart) uart supply current (4) 4. data based on a differential i dd measurement between reset confi guration and a permanent uart data transmit sequence at 1mbauds. this measurement does not include the pad toggling consumption. 1.6 i dd(i2c) i2c supply current (5) 5. data based on a differential i dd measurement between reset configuration (i2c disabled) and a permanent i2c master communication at 100khz (data sent equal to 55h). this measurement includes the pad toggling consumption but not the external 10kohm external pull-up on clock and data lines. 0.3 i dd(adc) adc supply current when converting (6) 6. data based on a differential i dd measurement between reset configuration and continuous a/d conversions at 8 mhz in scan mode on 16 inputs configured as ain. 1.2 i dd(usb) usb supply current (7) note: v dd_io must be 3.3 v 10% 7. data based on a differential i dd measurement between reset configur ation and a running generic hid application. 0.90 i dd(can) can supply current (8) 8. data based on a differential idd measurement between reset configuration (can disabled) and a permanent can data transmit sequence in loopback m ode at 1mhz. this measurement does not include the pad toggling consumption. 2.8 electrical parameters str750fxx str751fxx str752fxx str755fxx 44/81 5.3.5 clock and timi ng characteristics xt1 external clock source subject to general operating conditions for v dd_io , and t a . table 20. xt1 external clock source symbol parameter conditions (1) (2) 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. min typ max unit f xt1 external clock source frequency see figure 20 460mhz v xt1h xt1 input pin high level voltage 0.7xv dd_io v dd_io v v xt1l xt1 input pin low level voltage v ss 0.3xv dd_io t w(xt1h) t w(xt1l) xt1 high or low time (3) 3. data based on design simulation and/or technology characteristics, not tested in production. 6 ns t r(xt1) t f(xt1) xt1 rise or fall time (3) 5 i l xtx input leakage current v ss v in v dd_io 1 a str750fxx str751fxx str752fxx str755fxx electrical parameters 45/81 xrtc1 external clock source subject to general operating conditions for v dd_io , and t a . figure 20. typical application with an external clock source table 21. xrtc1 external clock source symbol parameter conditions (1) 1. data based on typical application software. min typ max unit f xrtc1 external clock source frequency see figure 20 32.768 500 khz v xrtc1h xrtc1 input pin high level voltage 0.7xv dd_io v dd_io v v xrtc1l xrtc1 input pin low level voltage v ss 0.3xv dd_io t w(xrtc1h) t w(xrtc1l) xrtc1 high or low time (2) 2. data based on design simulation and/or technology characteristics, not tested in production. 900 ns t r(xrtc1) t f(xrtc1) xrtc1 rise or fall time (2) 50 i l xrtcx input leakage current v ss v in v dd_i o 1 a xt1 xt2 f osc4m external str750 clock source v xt1l v xt1h t r(xt1) t f(xt1) t w(xt1h) t w(xt1l) i l 90% 10% t xt1 hi-z electrical parameters str750fxx str751fxx str752fxx str755fxx 46/81 4/8 mhz crystal / ceramic resonator oscillator (xt1/xt2) the str750 system clock or the input of the pll can be supplied by a osc4m which is a 4 mhz clock generated from a 4 mhz or 8 mhz cryst al or ceramic resonator. if using an 8 mhz oscillator, software set the xtdiv bit to enable a divider by 2 and generate a 4 mhz osc4m clock. all the information given in this paragraph are based on product characterisation with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). figure 21. typical application with a 4 or 8 mhz crystal or ceramic resonator table 22. 4/8 mhz crystal / ceramic resonator oscillator (xt1/xt2) (1) symbol parameter conditions min typ max unit f osc4m oscillator frequency 4 mhz crystal/resonator oscillator connected on xt1/xt2 xtdiv=0 or 8 mhz crystal/resonator oscillator connected on xt1/xt2 xtdiv=1 4mhz r f feedback resistor 200 240 270 k ? c l1 (2) c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) (3) r s =200 ? 60 pf i 2 xt2 driving current v dd_io =3.3 v or 5.0 v 425 a t su(osc4m) (4) startup time at v dd_io power-up 1 ms 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. for c l1 and c l2 it is recommended to use high-qualit y ceramic capacitors in the 5-pf to 25-pf range (typ.) designed for high-frequency applications and selected to match th e requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer ty pically specifies a load capacitance wh ich is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). 3. the relatively low value of the rf resistor offers a good protection against issues resu lting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. 4. t su(osc4m) is the typical start-up time measured from the moment v dd_io is powered (with a quick v dd_io ramp-up from 0 to 3.3v (<50 s) to a stabilized 4mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly wi th the crystal/ceramic resonator manufacturer. xt2 xt1 f osc4m c l1 c l2 i 2 r f str75x resonator when resonator with integrated capacitors v dd /2 ref feedback loop linear amplifier xtdiv /2 str750fxx str751fxx str752fxx str755fxx electrical parameters 47/81 osc32k crystal / ceramic resonator oscillator the str7 rtc clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are based on pr oduct characterisation with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). figure 22. typical application with a 32.768 khz crystal or ceramic resonator pll characteristics pll jitter terminology self-referred single period jitter (period jitter) period jitter is defined as the difference of the maximum period (t max ) and minimum period (t min ) at the output of the pll where t max is the maximum time difference between 2 consecutive clock rising edges and t min is the minimum time difference between 2 consecutive clock rising edges. see figure 23 self-referred long term jitter (n period jitter) self-referred long term jitter is defined as the difference of the maximum period (t max ) and minimum period (t min ) at the output of the pll where t max is the maximum time table 23. osc32k crystal / ceramic resonator oscillator symbol parameter conditions min typ max unit f osc32k oscillator frequency 32.768 khz r f feedback resistor v dd_io =3.3 v or 5.0 v 270 310 370 k ? c l1 c l2 recommended load capacitance versus equivalent se rial resistance of the crystal or ceramic resonator (r s ) (1) r s =40k ? 12.5 15 pf i 2 xt2 driving current v dd_io =3.3 v or 5.0 v v in =v ss 15 a t su(osc32k) (2) startup time v dd_io is stabilized 2.5 s 1. the oscillator selection can be optimized in terms of s upply current using an high qual ity resonator with small r s value. refer to crystal/ceramic resonator manufacturer for more details 2. t su(osc32k) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 khz oscillation is reached. this value is measured for a st andard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer xrtc2 xrtc1 f osc32k c l1 c l2 i 2 r f str750 32 khz when resonator with integrated capacitors resonator feedback loop electrical parameters str750fxx str751fxx str752fxx str755fxx 48/81 difference between n+1 consecutive clock rising edges and t min is the minimum time difference between n+1 consecutive clock rising edges. n should be kept su fficiently large to have a long term jitter (ex: thousands). for n=1, this becomes the single period jitter. see figure 23 cycle-to-cycle jitter (n period jitter) this corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs. jitter(cycle-t o-cycle) = max(tcycle n- tcycle n-1) for n=1 to n. see figure 24 figure 23. self-referred jitter (single and long term) figure 24. cycle-to-cycle jitter ideal ck_pll trigger point actual ck_pll nn+1 n+n --- long term jitter t single period jitter ideal ck_pll actual ck_pll nn+1 t tcycle 1 tcycle 2 n+2 --- tcycle n-1 n+n str750fxx str751fxx str752fxx str755fxx electrical parameters 49/81 pll characteristics subject to general operating conditions for v dd_io , and t a . internal rc oscillators (freeosc & lposc) subject to general operating conditions for v dd_io , and t a . table 24. pll characteristics symbol parameter test conditions value unit min typ max (1) 1. data based on product characterisation, not tested in production. f pll_in pll input clock 4.0 mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock f pll_in x 24 165 mhz f vco vco frequency range when pll operates (locked) 336 960 mhz t lock pll lock time 300 s ? t jitter1 (2)(3) 2. refer to jitter terminology in : pll characteristics on page 47 for details on how jitter is specified. 3. the jitter specification holds true only up to 50mv (peak-to-peak) noise on v dda_pll and v 18 supplies. jitter will increase if the noise is more than 50mv. in addition, it assumes that the input clock has no jitter. single period jitter (+/-3 peak to peak) f pll_in = 4 mhz (4) v dd_io is stable 4. the pll parameters (mx1, mx0, presc1, pres c2) must respect the constraints described in : pll characteristics on page 47 . +/-250 ps ? t jitter2 (2)(3) long term jitter (+/-3 peak to peak) f pll_in = 4 mhz (4) v dd_io is stable +/-2.5 ns ? t jitter3 (2)(3) cycle to cycle jitter (+/-3 peak to peak) f pll_in = 4 mhz (4) v dd_io is stable +/-500 ps table 25. internal rc oscillators (freeosc & lposc) symbol parameter conditions min typ max unit f ck_freeosc freeosc oscillator frequency 3 5 8 mhz f ck_lposc lposc oscillator frequency 150 300 500 khz electrical parameters str750fxx str751fxx str752fxx str755fxx 50/81 5.3.6 memory characteristics flash memory subject to general operating conditions for v dd_io and v 18 , t a = -40 to 105 c unless otherwise specified. table 26. flash memory characteristics symbol parameter test conditions value unit typ max (1) 1. data based on characterisa tion not tested in production t pw word program 35 s t pdw double word program 60 s t pb0 bank 0 program (256k) single word programming of a checker-board pattern 24.9 (2) 2. 10k program/erase cycles. s t pb1 bank 1 program (16k) single word programming of a checker-board pattern 125 224 (2) ms t es sector erase (64k) not preprogrammed (all 1) preprogrammed (all 0) 1.54 1.176 2.94 (2) 2.38 (2) s t es sector erase (8k) not preprogrammed (all 1) preprogrammed (all 0) 392 343 560 (2) 532 (2) ms t es bank 0 erase (256k) not preprogrammed (all 1) preprogrammed (all 0) 8.0 6.6 13.7 11.2 s t es bank 1 erase (16k) not preprogrammed (all 1) preprogrammed (all 0) 0.9 0.8 1.5 1.3 s t rpd recovery when disabled 20 s t psl program suspend latency 10 s t esl erase suspend latency 300 s table 27. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. data based on characterisa tion not tested in production. typ max n end_b0 endurance (bank 0 sectors) 10 kcycles n end_b1 endurance (bank 1 sectors) 100 kcycles y ret data retention t a =85 c 20 years t esr erase suspend rate min time from erase resume to next erase suspend 20 ms str750fxx str751fxx str752fxx str755fxx electrical parameters 51/81 5.3.7 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 28. emc characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd_io = 3.3 v or 5 v, t a = +25 c, f ck_sys = 32 mhz conforms to iec 1000-4-2 class a v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd_io = 3.3 v or 5 v, t a = +25 c, f ck_sys = 32 mhz conforms to iec 1000-4-4 class a electrical parameters str750fxx str751fxx str752fxx str755fxx 52/81 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the board and the loading of each pin. absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electro-static discharge (esd) electro-static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. table 29. emi characteristics symbo l parameter conditions monitored frequency band max vs. [f osc4m /f hclk ] unit 4/32mhz 4/60mhz s emi peak level flash devices: v dd_io = 3.3 v or 5 v, t a = +25 c, lqfp64 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 22 26 db v 30 mhz to 130 mhz 31 26 130 mhz to 1 ghz 19 23 sae emi level >4 >4 - table 30. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on product characterisation, not tested in production. unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 2000 v v esd(mm) electro-static discharge voltage (machine model) 200 v esd(cdm) electro-static discharge voltage (charge device model) 750 str750fxx str751fxx str752fxx str755fxx electrical parameters 53/81 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. table 31. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = +25 c t a = +85 c t a = +105 c class a dlu dynamic latch-up class v dd = 5.5 v, f osc4m = 4 mhz, f ck_sys = 32 mhz, t a = +25 c class a electrical parameters str750fxx str751fxx str752fxx str755fxx 54/81 5.3.8 i/o port pin characteristics general characteristics subject to general operating conditions for v dd_io and t a unless otherwise specified. table 32. general characteristics i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 0.8 v v ih input high level voltage 2 v hys schmitt trigger voltage hysteresis (1) 1. hysteresis voltage between schm itt trigger switching levels. 400 mv i inj(pin) injected current on any i/o pin 4 ma i inj(pin (2) 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd_io while a negative injection is induced by v in electrical parameters str750fxx str751fxx str752fxx str755fxx 56/81 table 33. output driving current i/o output drive characteristics for v dd_io = 3.0 to 3.6 v and en33 bit =1 or v dd_io = 4.5 to 5.5 v and en33 bit =0 i/o type symbol parameter conditions min max unit o2 v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in section 5.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss_io . output low level voltage for a standard i/o pin when 8 pins are sunk at same time i io =+2 ma 0.4 v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in section 5.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd_io . output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-2 ma v dd_io -0.8 o4 v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time i io =+4 ma 0.4 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-4 ma v dd_io -0.8 o8 v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time i io =+8 ma 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+20 ma, t a 85c t a 85c 1.3 1.5 i io =+8 ma 0.4 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-8 ma v dd_io -0.8 str750fxx str751fxx str752fxx str755fxx electrical parameters 57/81 output speed subject to general operating conditions for v dd_io and t a unless otherwise specified. figure 26. i/o output speed definition table 34. output speed i/o dynamic characteristics for v dd_io = 3.0 to 3.6v and en33 bit =1 or v dd_io = 4.5 to 5.5v and en33 bit =0 i/o type symbol parameter conditions min typ max unit o2 f max(io)out maximum frequency (1) 1. the maximum frequency is defined as described in figure 26 . c l =50 pf 10 mhz t f(io)out output high to low level fall time (2) 2. data based on product characterisation, not tested in production. c l =50 pf between 10% and 90% 30 ns t r(io)out output low to high level rise time (2) 33 o4 f max(io)out maximum frequency (1) c l =50 pf 25 mhz t f(io)out output high to low level fall time (2) c l =50 pf between 10% and 90% 12 ns t r(io)out output low to high level rise time (2) 14 o8 f max(io)out maximum frequency (1) c l =50pf 40 mhz t f(io)out output high to low level fall time (2) c l =50 pf between 10% and 90% 6 ns t r(io)out output low to high level rise time (2) 6 10% t 90% 50% t r(io)out output external on 50pf maximum frequency is achieved if (t r + t f ) (2/3)t and if the duty cycle is (45-55%) 10% 50% 90% t r(io)out when loaded by 50pf electrical parameters str750fxx str751fxx str752fxx str755fxx 58/81 nrstin and nrstout pins nrstin pin input driver is ttl/lvttl as for all gp i/os. a permanent pull-up is present which is the same as r pu (see : general characteristics on page 54 ) nrstout pin output driver is equivalent to the o2 type driver except that it works only as an open-drain (the p-mos is de-activated). a permanent pull-up is present which is the same as r pu (see : general characteristics on page 54 ) subject to general operating conditions for v dd_io and t a unless otherwise specified. table 35. nrstin and nrstout pins symbol parameter conditions min typ 1) max unit v il(nrstin) nrstin input low level voltage (1) 1. data based on product characterisation, not tested in production. 0.8 v v ih(nrstin) nrstin input high level voltage (1) 2 v hys(nrstin) nrstin schmitt trigger voltage hysteresis (2) 2. hysteresis voltage between schm itt trigger switching levels. 400 mv v ol(nrstin) nrstout output low level voltage (3) 3. the i io current sunk must always respect the absolute maximum rating specified in section 5.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . i io =+2 ma 0.4 v r pu(nrstin) nrstin weak pull-up equivalent resistor (4) 4. the r pu pull-up equivalent resistor ar e based on a resistive transistor v in = v ss v dd_io =3.3 v 25 50 100 k ? v dd_io =5 v 20 31 100 k ? t w(rstl)out generated reset pulse duration (visible at nrstout pin) (5) 5. to guarantee the reset of the device, a minimum pulse of 15 s has to be applied to the internal reset. at v dd_io power-up, the built-in reset stretcher may not generate the 15 s pulse duration while once v dd_io is established, an external reset pulse will be inter nally stretched up to 15 s thanks to the reset pulse stretcher. internal reset source 15 20 s t h(rstl)in external reset pulse hold time at nrstin pin (6) 6. the reset network (the resistor and two capacitors) pr otects the device against par asitic resets, especially in noisy environments. at v dd_io power-up (5) 20 s when v dd_io is established (5) 1 s t g(rstl)in maximum negative spike duration filtered at nrstin pin (7) 7. in fact the filter is made to ignore all incoming pulses with short duration: - all negative spikes with a duration less than 150 ns are filtered - all trains of negative spikes with a ratio of 1/2 are filtered. this means that all spikes with a maximum duration of 150 ns with minimum interval between spikes of 75 ns are filtered. data guaranteed by design, not tested in production. the time between two spikes must be higher than 1/2 of the spike duration. 150 ns str750fxx str751fxx str752fxx str755fxx electrical parameters 59/81 figure 27. recommended nrstin pin protection 1. the user must ensure that the level on the nrstin pin can go below the v il(nrstin) max. level specified in nrstin and nrstout pins on page 58 . otherwise the reset will not be taken into account internally. 0.01 f external reset circuit nrstin str7x pulse generator filter r pu v dd_io watchdog reset internal reset nrstout rsm reset software reset v dd_io filter to reset other chips r pu electrical parameters str750fxx str751fxx str752fxx str755fxx 60/81 5.3.9 tb and tim ti mer characteristics subject to general operating conditions for v dd_io , f ck_sys , and t a unless otherwise specified. refer to section 5.3.8: i/o port pin characteristics on page 54 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). table 36. tb and tim timers symbol parameter conditions min typ max unit t w(icap)in input capture pulse time tim0,1,2 2 t ck_tim t res(tim) timer resolution time (1) 1. take into account the frequency limitation due to the i/o speed capability when outputting the pwm to i/o pin, described in : output speed on page 57 . tb f ck_tim(max) = f ck_sys 1t ck_tim f ck_tim = f ck_sys = 60 mhz 16.6 (1) ns tim0,1,2 f ck_tim(max) = f ck_sys 1t ck_tim f ck_tim = f ck_sys = 60mhz 16.6 (1) ns f ext timer external clock frequency on ti1 or ti2 tim0,1,2 f ck_tim(max) = f ck_sys 0f ck_tim /4 mhz f ck_tim = f ck_sys = 60 mhz 015mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected (16-bit prescaler) tb 1 65536 t ck_tim f ck_tim = f ck_sys = 60 mhz 0.0166 1092 s tim0,1,2 1 65536 t ck_tim f ck_tim = f ck_sys = 60 mhz 0.0166 1092 s t max_count maximum possible count tb 65536x65536 t ck_tim f ck_tim = f ck_sys = 60 mhz 71.58 s tim0,1,2 65536x65536 t ck_tim f ck_tim = f ck_sys = 60 mhz 71.58 s str750fxx str751fxx str752fxx str755fxx electrical parameters 61/81 table 37. pwm timer (pwm) symbol parameter cond itions min typ max unit t res(pwm) pwm resolution time f ck_tim(max) = f ck_sys 1t ck_tim f ck_tim = f ck_sys = 60 mhz 16.6 (1) ns res pwm pwm resolution 16 bit v os (1) 1. take into account the frequency limitation due to the i/o speed capability when outputting the pwm to an i/o pin, as described in : output speed on page 57 . pwm/dac output step voltage v dd_io =3.3 v, res=16-bits 50 (1) v v dd_io =5.0 v, res=16-bits 76 (1) v t counter timer clock period when internal clock is selected 1 65536 t ck_tim f ck_tim =60 mhz 0.0166 1087 s t max_count maximum possible count 65536x 65536 t ck_tim f ck_tim = f ck_sys = 60 mhz 71.58 s electrical parameters str750fxx str751fxx str752fxx str755fxx 62/81 5.3.10 communication interface characteristics ssp synchronous serial peripheral in master mode (spi or ti mode) general operating conditions: v 33 , 3.0v to 3.3v, v18 =1.8v, c l 45 pf. table 38. ssp master mode characteristics (1) 1. data based on characterisation results, not tested in production. symbol parameter conditions min max unit f sck spi clock frequency (2) 2. max frequency for the 2 ssps is f pclk /2; f pclk max = 32 mhz. this takes into account the frequency limitation due to i/o speed capability. ssp0 uses io4 type while ssp1 uses io2 type i/os. ssp0 16 mhz ssp1 8 t r(sck) spi clock rise time ssp0 14 ns ssp1 33 t f(sck) spi clock fall time ssp0 11 ssp1 30 t w(sckh) t w(sckl) sck high and low time ssp0 19 ssp1 30 t nsslqv nss low to data output mosi valid time ssp0 0.5t sck +15ns ssp1 0.5t sck +30ns t scknssh sck last edge to nss high cpha = 0 ssp0 0.5t sck +15ns ssp1 0.5t sck +30ns cpha = 1 ssp0 t sck +15ns ssp1 t sck +30ns t sckqv sck trigger edge to data output mosi valid time ssp0 15 ssp1 30 t sckqx sck trigger edge to data output mosi invalid time ssp0 0 ssp1 0 t su data input (miso) setup time w.r.t sck sampling edge ssp0 25 ssp1 25 t h data input (miso) hold time w.r.t sck sampling edge ssp0 0 ssp1 0 str750fxx str751fxx str752fxx str755fxx electrical parameters 63/81 figure 28. spi configuration - master mode, single transfer figure 29. spi configuration - master mode, continous transfer, cpha=0 figure 30. spi configuration - master mode, continous transfer, cpha=1 nss output sck output cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(miso) t su(miso) t sckqv t sckqx msb in msb out bit in bit out lsb out lsb in cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) t nsslqv t scknssh (cpha=0) sample edge trigger edge sample edge trigger edge trigger edge trigger edge sample edge sample edge t sckqx t scknssh (cpha=1) 1 or 0 dont care dont care 1 or 0 nss output sample mosi output miso input trigger msb in msb out sample trigger sample trigger sample trigger sample trigger lsb in lsb out sample trigger msb in msb out sample dont care dont care 1.5*t c(sck) t c(sck) sck output cpol=0 cpol=1 frame 1 frame 2 1 or 0 t nsslqv t nsslqv nss output trigger mosi output miso input sample msb in msb out trigger sample trigger sample trigger samlpe trigger sample lsb in lsb out trigger sample msb in msb out trigger dont care t c(sck) sck output cpol=0 cpol=1 frame 1 frame 2 sample trigger sample trigger 1 or 0 electrical parameters str750fxx str751fxx str752fxx str755fxx 64/81 figure 31. ti configuration - master mode, single transfer figure 32. ti configuration - master mode, continous transfer nss mosi miso t c(sck) t w(sckh) t w(sckl) t h(miso) t su(miso) t sckqv t sckqx t r(sck) t f(sck) trigger edge sample edge sck dont care msb in trigger edge sample edge output output input output trigger edge sample edge msb out lsb in lsb out dont care 1 or 0 nss output mosi output miso input msb in msb out trigger sample trigger sample trigger sample trigger lsb in lsb out msb in msb out dont care t c(sck) t c(sck) frame 1 frame 2 sck output 1 or 0 sample trigger sample trigger sample trigger sample trigger sample lsb in lsb out dont care str750fxx str751fxx str752fxx str755fxx electrical parameters 65/81 ssp synchronous serial peripheral in slave mode (spi or ti mode) subject to general operating conditions with c l 45 pf figure 33. spi configuration, slave mode with cpha=0, single transfer table 39. ssp slave mode characteristics (1) 1. data based on characterisation results, not tested in production. symbol parameter conditions min max unit f sck spi clock frequency ssp0 2.66 mhz (f plck /12) mhz ssp1 t su(nss) nss input setup time w.r.t sck first edge ssp0 0 ns ssp1 0 t h(nss) nss input hold time w.r.t sck last edge ssp0 t pclk +15ns ssp1 t pclk +15ns t nsslqv nss low to data output miso valid time ssp0 2t pclk 3t pclk +30 ns ssp1 2t pclk 3t pclk +30 ns t nsslqz nss low to data output miso invalid time ssp0 2t pclk 3t pclk +15 ns ssp1 2t pclk 3t pclk +15 ns t sckqv sck trigger edge to data output miso valid time ssp0 15 ssp1 30 t sckqx sck trigger edge to data output miso invalid time ssp0 2t pclk ssp1 2t pclk t su(mosi) mosi setup time w.r.t sck sampling edge ssp0 0 ssp1 0 t h(mosi) mosi hold time w.r.t sck sampling edge ssp0 3t pclk +15 ns ssp1 3t pclk +15 ns nss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t sckqv(miso) t su(si) t h(si) msb out msb in bit out lsb in lsb out cpol=0 cpol=1 t su(nss) t h(nss) t sckqx(miso) bit1 in sample edge trigger edge trigger edge t nsshqz z t nsslqv sample edge z dont care dont care electrical parameters str750fxx str751fxx str752fxx str755fxx 66/81 figure 34. spi configuration - slave mode with cpha=0, continous transfer figure 35. spi configuration, sla ve mode with cpha=1, single transfer figure 36. spi configuration - slave mode with cpha=1, continous transfer nss input sample mosi input miso output trigger msb out msb in sample trigger sample trigger sample trigger sample trigger lsb out lsb in sample trigger msb out msb in sample 1.5*t c(sck) t c(sck) sck input cpol=0 cpol=1 frame 1 frame 2 dont care z t nsslqv 1.5*t c(sck) z t nsslqv t nshqz dont care nss input sck input cpha=1 mosi input miso output cpha=1 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t sckqv(miso) t su(si) t h(si) msb out msb in bit out lsb in lsb out cpol=0 cpol=1 t su(nss) t h(nss) bit1 in trigger edge sample edge sample edge t nsshqx z t nsslqv t sckqx(miso) trigger edge z t nsshqz dont care dont care nss output trigger mosi output miso input sample msb in msb out trigger sample trigger sample trigger samlpe trigger sample lsb in lsb out trigger sample msb in msb out trigger dont care t c(sck) sck output cpol=0 cpol=1 frame 1 frame 2 sample trigger sample trigger 1 or 0 str750fxx str751fxx str752fxx str755fxx electrical parameters 67/81 figure 37. ti configuration - slave mode, single transfer figure 38. ti configuration - slave mode, continous transfer nss miso mosi t c(sck) t w(sckh) t w(sckl) t h(mosi) t su(mosi) t sckqv t sckqx t r(sck) t f(sck) trigger edge sample edge sck dont care msb in trigger edge sample edge input input input output trigger edge sample edge msb out lsb in lsb out dont care t su(nss) t c(sck) /2 z t sckqz t c(sck) /2 z 1 or 0 nss output miso output mosi input msb in msb out trigger sample trigger sample trigger sample trigger lsb in lsb out msb in msb out dont care t c(sck) t c(sck) frame 1 frame 2 sck output 1 or 0 sample trigger sample trigger sample trigger sample trigger sample lsb in lsb out dont care t su(nss) t h(nss) electrical parameters str750fxx str751fxx str752fxx str755fxx 68/81 smi - serial memory interface subject to general operating conditions with c l 30 pf. figure 39. smi timing diagram i 2 c - inter ic control interface subject to general operating conditions for v dd_io , f pclk , and t a unless otherwise specified. the i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: restriction: the i/o pins which sda and scl are mapped to are not ?true? open- drain: when configured as open-drain, the pmos connected between the i/o pin and v dd_io is disabled, but it is still present. al so, there is a protection diode between the i/o pin and v dd_io . consequently, when using this i 2 c in a multi-master network, it is table 40. smi characteristics (1) 1. data based on characterisation results, not tested in production. symbol parameter conditions min max unit f smi_ck smi clock frequency 32 (2)(3) 2. max. frequency = f pclk /2 = 64/2 = 32 mhz. 3. valid for all temperature ranges: -40 to 105 c, with 30 pf load capacitance. mhz 48 (4) 4. valid up to 60 c, with 10 pf load capacitance. t r(smi_ck) smi clock rise time 10 ns t f(smi_ck) smi clock fall time 8 t v(smi_dout) data output valid time 10 t h(smi_dout) data output hold time 0 t v(smi_cssx) css output valid time 10 t h(smi_cssx) css output hold time 0 t su(smi_din) data input setup time 0 t h(smi_din) data input hold time 5 smi_dout output smi_din input t c(smi_ck) t w(smi_ckh) t w(smi_ckl) t h(smi_din) t su(smi_din) t v(smi_dout) t h(smi_dout) msb in msb out bit6 in bit6 out lsb out lsb in t r(smi_ck) t f(smi_ck) smi_ck output smi_cssx output t v(smi_css) t h(smi_css) str750fxx str751fxx str752fxx str755fxx electrical parameters 69/81 not possible to power off the str7x while some another i 2 c master node remains powered on: otherwise, the str7x will be powered by the protection diode. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). figure 40. typical application with i 2 c bus and timing diagram 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . table 41. sda and scl characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f pclk , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300 ns for t he sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k ? sda strt75x scl v dd 100 ? 100 ? v dd 4.7k ? i 2 cbus electrical parameters str750fxx str751fxx str752fxx str755fxx 70/81 5.3.11 usb characteristics the usb interface is usb-if certified (full speed). figure 41. usb: data signal rise and fall time table 42. usb startup time symbol parameter conditions max unit t startup usb transceiver startup time 1 s table 43. usb characteristics usb dc electrical characteristics symbol parameter conditions min. (1)(2) 1. all the voltages are measured from the local ground potential. 2. it is important to be aware that the dp/dm pins are not 5 v tolerant. as a consequence, in case of a a shortcut with vbus (typ: 5.0v), the protection diodes of the dp/dm pins w ill be direct biased . this will not damage the device if not more than 50 ma is sunk for longer than 24 hours but the reliability may be affected. max. (1)(2) unit input levels v di differential input sensitivity i(dp, dm) 0.2 v v cm differential common mode range includes v di range 0.8 2.5 v se single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k ? to 3.6v (3) 3. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k ? to v ss (3) 2.8 3.6 table 44. usb: full speed electrical characteristics symbol parameter conditions min max unit driver characteristics: t r rise time (1) c l =50 pf 420ns t f fall time 1) c l =50 pf 4 20 ns differential data lines v ss t f t r crossover points v crs str750fxx str751fxx str752fxx str755fxx electrical parameters 71/81 t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v 1. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). table 44. usb: full speed electrical characteristics symbol parameter conditions min max unit electrical parameters str750fxx str751fxx str752fxx str755fxx 72/81 5.3.12 10-bit adc characteristics subject to general operating conditions for v dda_adc , f pclk , and t a unless otherwise specified. table 45. 10-bit adc characteristics symbol parameter conditions min typ (1) 1. unless otherwise specified, typical data are based on t a =25c. they are given only as design guidelines and are not tested. max unit f adc adc clock frequency 0.4 8 mhz v ain conversion voltage range (2) 2. calibration is needed once after each power-up. v ssa_adc v dda_adc v r ain external input impedance (3)(4) 3. c parasitic represents the capacitance of the pcb ( dependent on soldering and pcb layout quality) plus the pad capacitance (3 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 4. depending on the input signal variation (f ain ), c ain can be increased for stabilization time and reduced to allow the use of a larger serial resistor (r ain ). it is valid for all f adc frequencies 8 mhz. 10 k ? c ain external capacitor on analog input (3)(4) 6.8 pf i lkg induced input leakage current +400 a injected on any pin 1 a -400 a injected on any pin except specific adjacent pins in ta b l e 4 6 1 a -400a injected on specific adjacent pins in ta b l e 4 6 40 a c adc internal sample and hold capacitor 3.5 pf t cal calibration time f ck_adc =8 mhz 725.25 s 5802 1/f adc t conv total conversion time (including sampling time) f ck_adc =8 mhz 3.75 s 30 (11 for sampling + 19 for successive approximation) 1/f adc i adc sunk on v dda_adc 3.7 ma str750fxx str751fxx str752fxx str755fxx electrical parameters 73/81 adc accuracy vs. negative injection current injecting negative current on specific pins listed in ta bl e 4 6 (generally adjacent to the analog input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed. it is recommended to add a schottky diode (pin to ground) to pins which may potentially inject negative current. figure 42. typical application with adc analog power supply and reference pins the v dda_adc and v ssa_adc pins are the analog power supply of the a/d converter cell. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see : general pcb design guidelines on page 74 ). table 46. list of adjacent pins analog input related adjacent pins anone ain1/p0.03 none ain2/p0.12 p0.11 ain3/p0.17 p0.18 and p0.16 ain4/p0.19 p0.24 ain5/p0.22 none ain6/p0.23 p2.04 ain7/p0.27 p1.11 and p0.26 ain8/p0.29 p0.30 and p0.28 ain9/p1.04 none ain10/p1.06 p1.05 ain11/p1.08 p1.04 and p1.13 ain12/p1.11 p2.17 and p0.27 ain13/p1.12 none ain14/p1.13 p1.14 and p1.01 ain15/p1.14 none ainx str75xx v dd i l 1 a v t 0.6v v t 0.6v c adc 3.2pf v ain r ain 10-bit a/d conversion 2k ?( max ) c ain electrical parameters str750fxx str751fxx str752fxx str755fxx 74/81 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1 f and optionally, if needed 10 pf capacitors as close as possible to the str7 power supply pins and a 1 to 10 f ca pacitor close to the power source (see figure 43 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as v dda_adc is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs near the a/d input being converted. software filtering of spurious conversion results for emc performance reasons, it is recommended to filter a/d conversion outliers using software filtering techniques. figure 43. power supply filtering v ss v dd_io 0.1 f v dd str75xx v dda_adc v ssa_adc power supply source str7 digital noise filtering external noise filtering 1 to 10 f 0.1 f (3.3v or 5.0v) str750fxx str751fxx str752fxx str755fxx electrical parameters 75/81 figure 44. adc accura cy characteristics table 47. adc accuracy adc accuracy with f ck_sys = 20 mhz, f adc =8 mhz, r ain < 10 k ? this assumes that the adc is calibrated (1) 1. calibration is needed once after each power-up. symbol parameter conditions typ max unit |e t | total unadjusted error (2) (3) 2. refer to adc accuracy vs. negative injection current on page 73 3. adc accuracy vs. mco (main clock output): t he adc accuracy can be significantly degraded when activating the mco on pin p0.01 while converting an analog channel (especially t hose which are close to the mco pin). to avoid this, when an adc conversion is launched, it is st rongly recommended to disable the mco. v dda_adc =3.3 v 1 1.2 lsb v dda_adc =5.0 v 1 1.2 |e o | offset error (2) (3) v dda_adc =3.3 v 0.15 0.5 v dda_adc =5.0 v 0.15 0.5 e g gain error (2) (3) v dda_adc =3.3 v -0.8 -0.2 v dda_adc =5.0 v -0.8 -0.2 |e d | differential linearity error (2) (3) v dda_adc =3.3 v 0.7 0.9 v dda_adc =5.0 v 0.7 0.9 |e l | integral linearity error (2) (3) v dda_adc =3.3 v 0.6 0.8 v dda_adc =5.0 v 0.6 0.8 e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = vin (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dda v ssa package characteristics str750fxx str751fxx str752fxx str755fxx 76/81 6 package characteristics 6.1 package mechanical data figure 45. 64-pin low profile quad flat package (10x10) figure 46. 100-pin low profile flat package (14x14) dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 a a2 a1 c l1 l e e1 d d1 e b dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 100 h c l l 1 e b a a 2 a1 d d1 e e 1 str750fxx str751fxx str752fxx str755fxx package characteristics 77/81 figure 47. 64-low profile fine pitch ball grid array package figure 48. 100-low profile fine pitch ball grid array package figure 49. recommended pcb design rules (0.80/0.75mm pitch bga) dim. mm inches min typ max min typ max a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 7.750 8.000 8.150 0.305 0.315 0.321 d1 5.600 0.220 e 7.750 8.000 8.150 0.305 0.315 0.321 e1 5.600 0.220 e 0.720 0.800 0.880 0.028 0.031 0.035 f 1.050 1.200 1.350 0.041 0.047 0.053 ddd 0.120 0.005 number of pins n 64 dim. mm inches min typ max min typ max a 1.700 0.067 a1 0.270 0.011 a2 1.085 0.043 a3 0.30 0.012 a4 0.80 0.031 b 0.45 0.50 0.55 0.018 0.020 0.022 d 9.85 10.00 10.15 0.388 0.394 0.40 d1 7.20 0.283 e 9.85 10.00 10.15 0.388 0.394 0.40 e1 7.20 0.283 e 0.80 0.031 f 1.40 0.055 ddd 0.12 0.005 eee 0.15 0.006 fff 0.08 0.003 number of balls n 100 dpad dsm dpad 0.37 mm dsm 0.52 mm typ. (depends on solder mask registration tolerance solder paste 0.37 mm aperture diameter ? non solder mask defined pads are recommended ? 4 to 6 mils screen print package characteristics str750fxx str751fxx str752fxx str755fxx 78/81 6.2 thermal characteristics the average chip-junction temperature, t j must never exceed 125 c. the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja )(1) where: ?t a is the ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ?p d is the sum of p int and p i/o (p d = p int + p i/o ), ?p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. ?p i/o represents the power dissipation on input and output pins; most of the time for the applications p i/o < p int and may be neglected. on the other hand, p i/o may be significant if the device is config ured to drive continuously external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: ? k is a constant for the particular part, which may be determined from equation (3) by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a . table 48. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 100 - 14 x 14 mm / 0.5 mm pitch 46 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 c/w ja thermal resistance junction-ambient lfbga 64 - 8 x 8 x 1.7mm 58 c/w ja thermal resistance junction-ambient lfbga 100 - 10 x 10 x 1.7mm 41 c/w str750fxx str751fxx str752fxx str755fxx order codes 79/81 7 order codes table 49. order codes partnumber flash prog. memory (bank 0) kbytes package can periph usb periph temp. range str750fv0t6 64 lqfp100 14x14 yes yes -40 to +85c str750fv1t6 128 str750fv2t6 256 str750fv2h6 (1) 1. for other memory sizes, contact sales office. 256 lfbga100 10x10 str751fr0t6 64 lqfp64 10x10 - yes -40 to +85c str751fr1t6 128 str751fr2t6 256 str751fr2h6 (1) 256 lfbga64 8x8 str752fr0t6 64 lqfp64 10x10 yes - -40 to +85c str752fr1t6 128 str752fr2t6 256 str752fr2h6 (1) 256 lfbga64 8x8 str752fr0t7 64 lqfp64 10x10 yes - -40 to +105c str752fr1t7 128 str752fr2t7 256 str752fr2h7 (1) 256 lfbga64 8x8 str755fr0t6 64 lqfp64 10x10 - - -40 to +85c str755fr1t6 128 str755fr2t6 256 str755fr2h6 (1) 256 lfbga64 8x8 str755fv0t6 64 lqfp100 14x14 STR755FV1T6 128 str755fv2t6 256 str755fv2h6 (1) 256 lfbga100 10x10 revision history str750fxx str751fxx str752fxx str755fxx 80/81 8 revision history table 50. revision history date revision description of changes 25-sep-2006 1 initial release 30-oct-2006 2 added power consumption data for 5v operation in section 5 04-jul-2007 3 changed datasheet title from str750f to str750fxx str751fxx str752fxx str755xx. added table 1: device summary on page 1 added note 1 to ta bl e 6 added stop mode idd max. values in ta bl e 1 4 updated xt2 driving current in table 23. updated rpd in ta b l e 3 2 updated table 21: xrtc1 external clock source on page 45 updated table 34: output speed on page 57 added characteristics for ssp synchronous serial peripheral in master mode (spi or ti mode) on page 62 and ssp synchronous serial peripheral in slave mode (spi or ti mode) on page 65 added characteristics for smi - serial memory interface on page 68 added table 42: usb startup time on page 70 str750fxx str751fxx str752fxx str755fxx 81/81 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - 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